Compiler assisted parallelization and optimization for multicore architecture

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j thesis september 2015.pdf (2.74 MB)

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2014-01-08

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BITS, Pilani

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Supervisor: Prof. S. GURUNARAYANAN

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Electrical & Electronics Engineering, Architecture

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http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/4283

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Department of Electrical and Electronics Engineering

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