A Novel Design of Ternary Full Adder Using CNTFETs

Abstract

This paper proposes a novel design of pass transistor-based ternary full adder (TFA) cell using inherent binary nature (0, 1) of input carry in carbon nanotube field effect transistor (CNTFET) technology. A buffer circuit is added to get high performance without sacrificing the overall energy efficiency of the design. The use of pass transistor logic style leads to low power consumption. The proposed TFA is examined exhaustively, using Synopsys HSPICE simulator with 32 nm Stanford CNTFET model in various test conditions and at different supply voltages. The proposed design has high driving capability and is robust. At 0.9 V power supply, the proposed design shows 69 % reduction in power–delay product in comparison with its counterpart, recently published in the literature.