Performance Evaluation of CNTFET based Dynamic Dual Edge Triggered Register

Abstract

Carbon Nanotube Field-Effect Transistor (CNTFET) with 1-D band structure providing better electrostatic control and high mobility due to ballistic transport operation has proved to be a promising alternative to the conventional CMOS technology. This paper presents a design, performance evaluation and comparative analysis for CNTFET based Dynamic Dual Edge Triggered D-Flip flop (DFF). Hspice simulation results shows that the presented DFF consumes significantly lower power and delay than its CMOS counterpart at 32 nm technology. The performance analysis of Serial in serial out register (SISO) based on these DFFs shows 88% reductions in the power delay product.