A New XOR-FREE Approach to Implement Walsh Sequences

Abstract

This paper presents a new algorithm to construct a XOR-Free architecture of an area efficient Walsh generator. The approach completely removes the modulo-two operations required for extracting zero crossing and parity in the generation. In its place a new Transition Sequence based approach is introduced to obtain that string. The string then, becomes input to a triggered flip-flop and generate 2n Walsh sequences in dyadic ordering. The approach reduces the conventional sequential design to semi-sequential and thereby reduces the encoding/decoding cost with lesser design complexity. Results of the proposed architecture reduces the area up to 25–90% by extracting both the symmetry and state isomorphism. Further, it improves dynamic power consumption up to 3–60% with increasing sequence length as compare to conventional approach. The hardware co-simulation of the architecture is first validated and then implemented with Xilinx ZYNQ FPGA.