A Three-Stage Dynamic Comparator for SAR ADC Optimized for Reduced Kickback Noise and Ultra-Low Delay

Abstract

This paper presents a novel footless single clock-phase three-stage comparator with internally generated regenerative voltage signals for low kickback noise and high speed. The preamplifier and clocked latch topology of dynamic comparators are considered in this brief. The proposed design has been compared by analyzing and optimizing three state-of-the-art comparator designs: Modified StrongARM, Miyahara’s and Three-Stage. These designs are simulated using the 40nm CMOS technology process. The area of the proposed comparator is 28.025μm2. When simulated in the SPICE-based simulator HSPICE, under typical performance conditions of 0.9V supply voltage, 25∘C, 1 GHz operational frequency, typical process corner (tt), and 1mV differential voltage, the proposed comparator produces the best post-layout results, with a minimum delay of 59.9ps from meta-stability analysis, energy per comparison of 0.175pJ/comparison and a kickback noise of 44.55 μA. The proposed design also shows a significant improvement in the measured performance parameters over the other state-of-the-art dynamic comparators that have been discussed in this brief. The obtained results show that the proposed comparator is appropriate for 12-bit Successive Approximation Resister Analog-to-Digital Converters (SAR-ADCs) in IoT applications.