Design of a Low Power 11T-1MTJ Non-Volatile SRAM Cell with Half-Select Free Operation

Abstract

Over the past few decades, CMOS scaling has been a key driving factor to achieve faster, cheaper and denser digital systems. However, as the technology scales down, there is an exponential increase in leakage current which poses serious design challenges for low power system. SRAM being the biggest on-chip component, suffers from large static power dissipation which in turn significantly affects the overall performance of the system. In addition to large power consumption, SRAM cell also suffers from half-select disturbance issue which severely degrades the reliability of system. So, to address the aforementioned challenges, we review and compare the various existing SRAM cells in order to select the best SRAM cell design (TFC-9T) which offers advantages of low power and half-select disturbance free operation. To further reduce the static power consumption, we propose to modify the selected TFC-9T SRAM cell using emerging non-volatile magnetic tunnel junction (MTJ).