A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic

Abstract

A high-speed radix-64 parallel multiplier using novel reduced delay partial product generator is proposed. The use of radix-64 Booth encoder and selector for partial product generation by Sang-Hoon (Sang-Hoon Lee et al., 2002) reduces the number of partial product rows by six fold. The Booth selector selects one among X, 2X, 3X, 4X, 8X, 16X, 24X and 32X where X is the multiplicand. Before selection 3X computation must be completed which accounts for maximum delay because of carry propagation or carry look ahead addition of X and 2X. In this work this fundamental coefficient is generated as 4X-X using redundant binary (RB) arithmetic. This leads to zero delay for 3X computation as well as simplifies the partial product rows accumulation. This novel method of partial product generation decreases delay by 24% in comparison to last high-speed reported parallel multiplier (Sang-Hoon Lee et al., 2002) using radix-64 Booth encoding