A CMOS/MTJ Based Novel Non-volatile SRAM Cell with Asynchronous Write Termination for Normally OFF Applications

Abstract

Non-volatile SRAM (NV-SRAM) enables normally off computing while achieving faster power off/on time by storing the state in its locally embedded non-volatile elements. Emerging magnetic memory such as spin transfer torque magnetic tunnel junction (STT-MTJ) is preferred in the NV-SRAM design because of its attractive features like unlimited endurance, high density, scalability and CMOS compatibility. However, write operation in MTJ is stochastic which means duration of MTJ write is undeterministic. As a result, it suffers from reliability issue like write errors. Existing solution to reduce the write error rate mainly consist of increased write pulse duration which leads to high power consumption. However, if write completion could be detected on fly and write current could be cut-off immediately, energy consumption can be reduced by a large extent. Therefore, this work proposes a novel non-volatile SRAM cell with asynchronous write termination scheme. In the proposed NV-SRAM cell, write operation is continuously monitored and terminated as soon as MTJ is switched to the required state. Our analysis indicates that the proposed cell achieves reduction in write power by 23% when compared with the cell without write assist. Moreover, the proposed write termination circuit achieves 2.52–14% more power saving when compared to existing write termination circuits.