Effect of trap states at the oxide-silicon interface in polycrystalline silicon thin-film transistors

Abstract

This work presents the study of the effect of trap states at the oxide-silicon interface in lightly doped polycrystalline silicon thin-film transistors with large grains. In this study, it is assumed that the oxide-silicon interface traps are evenly distributed throughout the interface region and single grain boundary is present in the channel of poly-Si TFT. It is shown that improved device characteristics can be obtained by reducing the gate oxide thickness. It is also observed that as gate oxide thickness decreases for a constant value of trap state density in the oxide-silicon interface, the gate voltage required for channel formation is lowered and leads to a decrease in threshold voltage of the device. Calculated and experimental results are also found to be well consistent with each other.