Comparative Analysis of D/A Converter Architectures for SAR ADC

Abstract

This study gives an in-depth analysis of the architectures utilized in the analog-to-digital conversion process. The paper encompasses the design, performance, and suitability of the binary-weighted (charge distribution), R-2R ladder, and C-2C Digital-to-Analog (D/A) Converter architectures. This paper's discussed D/A converter architectures are simulated through the cadence tool using 180 nm CMOS technology. Based on comparative performance analysis, the C-2C D/A converter gives optimum results in terms of power, speed, DNL, INL, and settling time while maintaining its resolution. C-2C D/A converter reported a 63.15% improvement in power consumption compared to R-2R DAC, DNL, and INL errors below 0.01 LSB.