Modelling of electrostatic discharge (ESD) protection circuits for CMOS ICS

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dc.contributor.authorGurunarayanan, S.
dc.date.accessioned2021-09-03T14:43:28Z
dc.date.available2021-09-03T14:43:28Z
dc.date.issued2000-01-03
dc.descriptionSupervisor: Dr. Chandra Shekharen_US
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/1904
dc.language.isoenen_US
dc.publisherBITS Pilanien_US
dc.subjectPhysicsen_US
dc.subjectElectrostatic Discharge (ESD)en_US
dc.subjectElectrothermal Simulationen_US
dc.titleModelling of electrostatic discharge (ESD) protection circuits for CMOS ICSen_US
dc.typeThesisen_US

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