Novel design of ternary magnitude comparator using CNTFETs

dc.contributor.authorGupta, Anu
dc.date.accessioned2023-02-10T10:52:40Z
dc.date.available2023-02-10T10:52:40Z
dc.date.issued2014
dc.description.abstractThis paper proposes a novel design of 1-bit ternary magnitude comparator (TMC) using carbon nano tube field effect transistors (CNTFETs). The proposed 1-bit TMC is designed for pass transistor logic style in order to achieve low transistor count. Further, proposed design is used in realization of n-bit TMC which utilizes static binary tree configuration to correct the voltage levels and minimizes the number of stages to get high performance. Synopsis Hspice simulation results demonstrate that the proposed TMC for 4-bit operand length is 15% faster or 14% energy efficient with 32% less number of transistors, in comparison with CNTFET-based designs, recently published in the literature.en_US
dc.identifier.urihttps://ieeexplore.ieee.org/document/7030447
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9159
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectCarbon nanotube (CNT) field effect transistor (CNTFET)en_US
dc.subjectTernary logicen_US
dc.subjectTernary magnitude comparator (TMC)en_US
dc.titleNovel design of ternary magnitude comparator using CNTFETsen_US
dc.typeArticleen_US

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