Comparative Analysis of ST, ECRL and Static Logic Style at Different Process Technologies

Abstract

In the lower VLSI process technologies, to design the low-power VLSI circuits selection of suitable logic style becomes important to minimize the chip’s power to meet the power density need with minimum sacrifice in the speed. This study’s emphasis is on the design and optimization of digital code converters. To compare propagation delay, power consumption and power delay product (PDP) at 32 nm and 22 nm process technologies, sub-threshold (ST) logic style implementations of Gray code to Binary code (GB), Binary code to Gray code (BG), and BCD code to Excess-3 code (BE3) code converters are used. These implementations are compared with Efficient Charge Recovery Logic (ECRL) and static CMOS logic style implementations