Electret mechanism, hysteresis, and ambient performance of sol-gel silica gate dielectrics in pentacene field-effect transistors

Abstract

The electret induced hysteresis was studied in sol-gel silica films that result in higher drain currents and improved device performance in pentacene field-effect transistors. Vacuum and ambient condition studies of the hysteresis behavior and capacitance-voltage characteristics on single layer and varying thicknesses of bilayer dielectrics confirmed that blocking layers of thermal oxide could effectively eliminate the electret induced hysteresis, and that thin (25nm) sol-gel silica dielectrics enabled elimination of nanopores thus realizing stable device characteristics under ambient conditions.