Circuit Performance Improvement Using PDSOI-DTMOS Devices with a Novel Optimal Sizing Scheme Considering Body Parasitics

Abstract

In sub-1V CNIOS technologies, the approach of increasing speed and reducing area of circuits with scaling is facing a severe challenge due to exponential increase in leakage currents. The DTMOS device has an ideal subthreshold slope and can be realized in mainstream CNIOS technologies that provide device isolation. PDSOI technology offers the desirable isolation of device bodies. However, the resistance and capacitance of body degrade the performance of PDSOI-DTMOS circuits. In order to maximize the performance of PDSOT-DTMOS circuits, we propose simple but accurate delay and input capacitance models and layout guidelines for DTMOS logic gates, which incorporate the effect of the body parasitics. We then use these models to optimize the sizing of PDSOI-DTMOS devices to maximize circuit performance. With this approach, we observe that DTNIOS offers a 60% reduction in leakage power for a given circuit speed in 50nm technology.