Current-Mode PMOS capacitance multiplier

Abstract

This paper presents a novel technique to achieve an effective capacitance, multiples of up to 40 times that of a capacitor embedded in electronic circuits thus minimizing the area of silicon die. The technique employed for multiplication is PMOS transistor based low-voltage cascode current mirroring consuming low-power. The proposed design, capable of achieving high multiplication factors, is simulated in Cadence using 180nm technology library. An application of the capacitance multiplier shifting the dominant pole by 254kHz of a 19.7dB gain common source amplifier is also presented.