Browsing by Author "Gupta, Anu"

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A 12.11 mW, 99 pJ/Conv.-Step SAR ADC with Optimal Power Efficiency for IoT
(IEEE, 2024-12) Gupta, Anu; Shekhar, Chandra
This brief presents a capacitive charge scaling DAC architecture with a two-phase non-overlapping clocking scheme to make an energy-efficient Successive Approximation Register (SAR) data converter for Internet-of-Things (IoT) applications. The proposed architecture comprises a Track & Hold (T/H), a Modified Strong Arm Latch comparator (MSAL), a SAR Control logic, and a digital-to-analog (D/A) converter. The proposed work is simulated using Cadence Virtuoso in TSMC 180 nm and achieves a minimum sampling rate of 1 MS/s and power consumption of 12.11 mW. To address the effects of process variations and mismatches on ADC performance, this paper conducts a thorough 500-point Monte Carlo (MC) simulation of the proposed SAR ADC circuit. The measured results show a Signal-to-Noise Ratio (SNR) of 47.81 dB, a Spurious-Free Dynamic Range (SFDR) of 54.32 dB, and ENOB of 7.65 Bits.
Accurate Iris Localization Using Edge Map Generation and Adaptive Circular Hough Transform for Less Constrained Iris Images
(IJECE, 2016-08) Gupta, Anu; Asati, Abhijit
This paper proposes an accurate iris localization algorithm for the iris images acquired under near infrared (NIR) illuminations and having noise due to eyelids, eyelashes, lighting reflections, non-uniform illumination, eyeglasses and eyebrow hair etc. The two main contributions in the paper are an edge map generation technique for pupil boundary detection and an adaptive circular Hough transform (CHT) algorithm for limbic boundary detection, which not only make the iris localization more accurate but faster also. The edge map for pupil boundary detection is generated on intersection (logical AND) of two binary edge maps obtained using thresholding, morphological operations and Sobel edge detection, which results in minimal false edges caused by the noise. The adaptive CHT algorithm for limbic boundary detection searches for a set of two arcs in an image instead of a full circle that counters iris-occlusions by the eyelids and eyelashes. The proposed CHT and adaptive CHT implementations for pupil and limbic boundary detection respectively use a two-dimensional accumulator array that reduces memory requirements. The proposed algorithm gives the accuracies of 99.7% and 99.38% for the challenging CASIA-Iris-Thousand (version 4.0) and CASIA-Iris-Lamp (version 3.0) databases respectively. The average time cost per image is 905 msec. The proposed algorithm is compared with the previous work and shows better results.
Analysis & implementation of ultra low-power 4-bit CLA in subthreshold regime
(IEEE, 2014) Gupta, Anu; Asati, Abhijit
The paper presents the analysis and implementation of ultra low-power, low voltage and low area 4-bit carry look ahead adder circuits. Sub-threshold design technique has been used to reduce the power consumption and area while maintaining low complexity of logic design in the proposed circuit. Simulation results illustrate the superiority of the circuits in sub-threshold region against the conventional low power design technique, in terms of power, area and power delay product (PDP). The CLA is implemented on TSMC 0.18μm process models in Cadence Virtuoso Schematic composer with improved driving ability and circuit robustness at 0.4V single ended supply voltage and simulations are carried out on Spectre S. The proposed 4-bit CLA can operate up to 5 MHz and used 0.035 μW of power and occupied an area of 60×92.5 μm 2 .
An asynchronous 8-bit 5 MS/s pipelined ADC for biomedical sensor based applications
(IEEE, 2013) Gupta, Anu
Integrated biomedical sensors are used in biomedical devices which monitor vital bio-signals such as ECG, EMG, AAP, etc., whose maximum frequency range up to few MHz. Such integrated systems require analog to digital converters with Megahertz conversion rate. This paper presents a novel architecture of asynchronous pipelined analog to digital converter with emphasis on elimination of external clock for integrated biomedical sensor based applications. The main innovative feature of the proposed pipelined ADC is that it operates without any external timing signal and behaves like a combinational logic for a given analog input. Complete digital conversion is obtained by asynchronously propagating the partial conversions and the residues through the various stages. The only requirement for the ADC is an external trigger signal from the sensors. The proposed 8 bit ADC implemented in UMC 0.18 μm CMOS technology has a sampling rate of 5 MHz, with power dissipation of 30 mW and has an active area of 0.8544 mm 2
Asynchronous 8-bit pipelined ADC for self-triggered sensor based applications
(IEEE, 2012) Gupta, Anu
This paper presents a novel architecture of Asynchronous Pipelined Analog to digital converter with emphasis on elimination of external clock for integrated self-triggered sensor based applications. The main innovative feature of the proposed pipelined ADC is that it operates without any external clock signal and performs conversion of the analog input like a combinational logic. Complete digital conversion is obtained by asynchronously propagating the partial conversions and the residues through the various stages. The only requirement for the ADC is an external trigger signal from the sensors. The proposed 8 bit ADC implemented in UMC 0.18um CMOS technology has a sampling rate of 5 MHz, with power dissipation of 30 mW and has an active area of 1.0506 mm 2 .
Automation of clock distribution network design for digital integrated circuits using divide and conquer technique
(Elsevier, 2006-07) Gupta, Anu
One of the most carefully engineered components of a digital integrated circuit is the clock distribution network. A clock is unarguably the most important signal and the network used for its distribution contributes to nearly half of the entire power dissipated by the IC. The design of a clock distribution network requires tremendous resources in terms of time and effort to achieve optimized results. This paper discusses the development of a new algorithm with smaller time complexity for automation of the design of clock distribution network that can greatly reduce the time and effort required, at the same time meeting the conditions set for delays and maximum allowable power dissipation.
Characterization of Logical Effort for Improved Delay
(Springer, 2013) Gupta, Anu
In this paper, an effort has been made to improve the delay of a gate by skewing the gates by choosing proper sizing. The expression for skewed logical effort has been derived for universal logic gates namely NOT, NAND and NOR for minimizing the delay. The validations for minimum delay through simulation was done on a chain of inverters. The improved skewed gates showed 10% - 20% delay reduction on a chain of inverters as compared with normal skewed gate, high and low skewed gates, whereas, an improvement of 20% - 25% when compared to skewed gates favoring a particular transition. All simulations are done using Spectre in Cadence environment in UMC90nm CMOS technology at 1V power supply.
CNTFET based design of content addressable memory cells
(IEEE, 2013) Gupta, Anu
Carbon Nanotube Field-Effect Transistor (CNTFET) with 1-D band structure providing high carrier velocity on account of ballistic transport operation and low OFF current capability has proved to be a promising alternative to the conventional CMOS technology. This paper presents novel designs of content addressable memory (CAM) cells using CNTFETs. A CAM performs parallel data comparison with data storage. Binary CAM (BCAM) performs exact-match searches while Ternary CAM (TCAM) provides an added flexibility of pattern matching with the use of don't care. HSPICE simulation results are reported to show that the three memory operations of the proposed CAM cells perform correctly at 0.9 V power supply. It is also shown that the presented BCAM and TCAM cell achieves a great improvement in search delay by 84% and 75% respectively compared to CNTFET based conventional cells.
Comparative Analysis of D/A Converter Architectures for SAR ADC
(IEEE, 2024-02) Gupta, Anu; Shekhar, Chandra
This study gives an in-depth analysis of the architectures utilized in the analog-to-digital conversion process. The paper encompasses the design, performance, and suitability of the binary-weighted (charge distribution), R-2R ladder, and C-2C Digital-to-Analog (D/A) Converter architectures. This paper's discussed D/A converter architectures are simulated through the cadence tool using 180 nm CMOS technology. Based on comparative performance analysis, the C-2C D/A converter gives optimum results in terms of power, speed, DNL, INL, and settling time while maintaining its resolution. C-2C D/A converter reported a 63.15% improvement in power consumption compared to R-2R DAC, DNL, and INL errors below 0.01 LSB.
Comparative Analysis of Phase/Frequency Detector in a Complete PLL System
(IEEE, 2023) Gupta, Anu; Shekhar, Chandra
In many integrated radio frequency (RF) transceivers, the phase-locked loop (PLL) serves as a frequency synthesizer. This work goes to test various different phase/frequency detector blocks with a standard charge pump and Voltage controlled oscillator design. These include the comparison of different phase-frequency detectors (PFD) based upon D-flipflops, latches (Latch PFD) & pass transistors (PTPFD) to the more complex Pre-charged PFD. The best results of the PFDs in the PLL system in order are Pre-charge PFD, PT-PFD, Latch PFD and D-flipflop PFD. A charge pump PLL (CPLL) with a frequency range of [80 MHz -800 MHz] is simulated using Cadence Virtuoso (Spectre) at 180nm technology (scl\_pdk) with 1.8 V supply voltage. The phase noise of the VCO is less than -50dBc/Hz at 10MHz and is closer to 110dBc/Hz at 1GHz.
A comparative analysis of power and delay optimise digital logic families for high performance system design
(Inder Science, 2013-12) Gupta, Anu
In this paper, we propose a high performance system design methodology taking the best average delay on prime. Our analysis method is based on the commonly used logical effort methodology, extended to the least delay to find the transistors sizing. Simulation results are tabulated using SPECTRE in 0.18 µm CMOS technology as applied to three different logic styles including static CMOS, pseudo-NMOS and skewed logic. We observe that NAND based pseudo-NMOS logic design having NMOS width as 1 µm exhibits least delay but with enormous power dissipation, evaluated by the tool, whereas, skewed logic style response is better in terms of total power. Thus, the method used accurately shows the trade-off in power-delay of a given circuit, allowing a designer to choose the most appropriate logic style.
A Comparison of Adiabatic Logic Circuit Techniques for an Energy Efficient 1-Bit Full Adder Design
(Taylor & Francis, 2016) Gupta, Anu
Power dissipation has become a critical design constraint in portable applications like a hand held computer due to limited battery life and reliability of integrated circuits. In this paper, a detailed comparison of five adiabatic logic families is carried out by simulation using SPICE. The simulation results are obtained for full adders, which are designed using the different design techniques with a view to design an energy efficient 1-bit full adder. The parameters compared are average energy consumption per addition, instantaneous peak power dissipation, number of transistors required, and operating frequency range. Average energy consumption per addition of full adders is found to vary with the variation in power-clock as well as input signal frequencies. An optimum value of power-clock frequency at which minimum energy consumption occurs at a fixed input signal frequency is obtained for all circuit techniques. Full adders circuits are designed using 0.5 μm CMOS technology.
A comprehensive survey on data converters for IOT applications: scope, issues, and future directions
(IEEE, 2025-03) Gupta, Anu; Shekhar, Chandra; Chamola, Vinay
Data converters significantly contribute to efficient and accurate data processing in Internet of Things (IoT) systems. As IoT expands into agriculture, industrial automation, and healthcare (AIH), precise and low-power data conversion has become crucial to support longer battery life and reliable performance in IoT devices. Efficient data converters are key to reducing energy use, especially in components like comparator circuits, which consume significant energy in successive approximation register analog-to-digital converters (SAR ADCs). This survey provides an in-depth review of recent developments in low-power data converter design, examining techniques that help reduce power consumption at various stages. It emphasizes advancements, such as energy scaling, dynamic voltage references, and architectural optimizations that enhance efficiency without compromising performance. A specific analysis of emerging technology trends, such as the application of machine learning in data converter design, is explored to stimulate further innovation. Machine learning (ML)-based optimization, including adaptive calibration, noise reduction, and real-time performance optimization, presents new opportunities for enhancing efficiency and accuracy while addressing critical design constraints in IoT applications. While quantum encryption offers promising advancements in securing IoT data transmission, a broader security perspective beyond encryption is necessary, including concerns, such as attack detection and data integrity, ensuring the robustness of IoT systems. This review also examines latency, signal integrity, and accuracy issues, offering a roadmap for next-generation converter designs and reducing power consumption in data converters, which are fundamental to enhancing the performance and lifespan of IoT devices.
Constant power consumption design of novel differential logic gate for immunity against differential power analysis
(IET, 2018-11) Gupta, Anu
Differential power analysis (DPA) method is frequently used for the non-invasive side-channel attack to hack into the system. This study proposes a novel DPA immune design of basic gates, which show the dense distribution of autocorrelation and strong salience strength around 60%. The design has a highly regular structure with exactly similar evaluation path for both differential outputs, AND–NAND, and OR–NOR which can be easily extended for n-bit inputs. The design effort is minimal as the structure is such that AND–NAND design can be used to obtain OR–NOR function by just changing the placement of inputs. These gates have 0.46× less propagation delay, and 3.7× higher power consumption in comparison to other published work. The designs are simulated using Cadence tool with TowerJazz CMOS 180 nm technology with a power supply of 1.8 V
Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology
(Springer, 2013) Gupta, Anu
Tradeoff between the power dissipation and speed is one of the major issues in modern VLSI circuit design. Improving the circuit speed methods typically lead to excessive power consumption. In this work, we explore the energy-delay design in CMOS circuits, to find gate sizes which produce the lowest possible energy and delay. Our analysis methods include delay minimization using logical effort, formulating energy relationship with logical effort model and then optimizing the energy-delay using optimization technique. Thus, we introduce the Energy-Delay-Gain (EDG) to measure the energy reduction rate for each delay increase that is acceptable by the designer. The simulation is done using Spectre in cadence environment in UMC90nm CMOS technology.
Current-Mode PMOS capacitance multiplier
(IEEE, 2017) Gupta, Anu
This paper presents a novel technique to achieve an effective capacitance, multiples of up to 40 times that of a capacitor embedded in electronic circuits thus minimizing the area of silicon die. The technique employed for multiplication is PMOS transistor based low-voltage cascode current mirroring consuming low-power. The proposed design, capable of achieving high multiplication factors, is simulated in Cadence using 180nm technology library. An application of the capacitance multiplier shifting the dominant pole by 254kHz of a 19.7dB gain common source amplifier is also presented.
Dedicated hardware architecture for localizing iris in VW images
(Elsevier, 2022-07) Asati, Abhijit; Gupta, Anu
This study presents dedicated hardware for iris localization that can be used as a coprocessor in the development of real-time and low-cost embedded iris biometric systems. Though the hardware architecture is described for iris localization in the visible wavelength (VW) images, the concept used can be applied to near infrared (NIR) images as well. In general, the architecture can be used for a class of iris localization algorithms based on the edge-map generation and circular Hough transform (CHT). The architecture presented here generates the edge-maps for limbic and pupil boundary detection using median filtering followed by Sobel edge detection; however, an additional reflection removal module is used for pupil boundary detection. Further, the CHT hardware module detects circle in each edge-map. The proposed architecture was implemented in programmable logic of the Zynq-7000 SoC device from Xilinx. This hardware implementation gives an iris localization accuracy of 98.43% and average processing time of 5.148 ms for UBIRIS.v1 VW database images (200 × 150 pixel). The algorithm used is suitable for less unconstrained and frontal-view iris images captured with subjects’ active participation; however, the images may contain non-ideal issues such as reflection and occlusion by eyelids and eyelashes.
Dedicated hardware architecture for localizing iris in VW images
(Elsevier, 2022-07) Asati, Abhijit; Gupta, Anu
This study presents dedicated hardware for iris localization that can be used as a coprocessor in the development of real-time and low-cost embedded iris biometric systems. Though the hardware architecture is described for iris localization in the visible wavelength (VW) images, the concept used can be applied to near infrared (NIR) images as well. In general, the architecture can be used for a class of iris localization algorithms based on the edge-map generation and circular Hough transform (CHT). The architecture presented here generates the edge-maps for limbic and pupil boundary detection using median filtering followed by Sobel edge detection; however, an additional reflection removal module is used for pupil boundary detection. Further, the CHT hardware module detects circle in each edge-map. The proposed architecture was implemented in programmable logic of the Zynq-7000 SoC device from Xilinx. This hardware implementation gives an iris localization accuracy of 98.43% and average processing time of 5.148 ms for UBIRIS.v1 VW database images (200 × 150 pixel). The algorithm used is suitable for less unconstrained and frontal-view iris images captured with subjects’ active participation; however, the images may contain non-ideal issues such as reflection and occlusion by eyelids and eyelashes.
Dedicated hardware architecture for localizing iris in VW images
(Elsevier, 2022-07) Asati, Abhijit; Gupta, Anu
This study presents dedicated hardware for iris localization that can be used as a coprocessor in the development of real-time and low-cost embedded iris biometric systems. Though the hardware architecture is described for iris localization in the visible wavelength (VW) images, the concept used can be applied to near infrared (NIR) images as well. In general, the architecture can be used for a class of iris localization algorithms based on the edge-map generation and circular Hough transform (CHT). The architecture presented here generates the edge-maps for limbic and pupil boundary detection using median filtering followed by Sobel edge detection; however, an additional reflection removal module is used for pupil boundary detection. Further, the CHT hardware module detects circle in each edge-map. The proposed architecture was implemented in programmable logic of the Zynq-7000 SoC device from Xilinx. This hardware implementation gives an iris localization accuracy of 98.43% and average processing time of 5.148 ms for UBIRIS.v1 VW database images (200 × 150 pixel). The algorithm used is suitable for less unconstrained and frontal-view iris images captured with subjects’ active participation; however, the images may contain non-ideal issues such as reflection and occlusion by eyelids and eyelashes.
Design & Analysis of Performance-efficient Comparator for IoT Application
(IEEE, 2022) Shekhar, Chandra; Gupta, Anu
The regenerative latch comparator prototype for high-speed up to 1 Giga Hertz analog-to-digital conversion is shown in this article. Cascading structure of different modules makes the proposed comparator a suitable choice for various converters like SAR, Pipelined, Flash, etc. The proposed comparator achieves efficiency in terms of propagation latency, power consumption, and area as compared to the present state of the art mentioned in this work. Additionally, it uses the cadence schematic editor tool to illustrate how the performance of a comparator changes depending on its common-mode voltage (Vcm) and input (Vid) on TSMC 180 nm CMOS technology.