Browsing by Author "Vidhyadharan, Sanjay"

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An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications
(Springer, 2019-11) Vidhyadharan, Sanjay
Adiabatic circuits are ideally suited for implementing RFID tags and biomedical sensors due to their ultra-low power requirements. This paper presents a novel Gate Overlap Tunnel FET (GOTFET) based Advanced Adiabatic Logic which consumes upto 67% lower power than the equivalent CMOS based Symmetric Pass Gate Adiabatic Logic (SPGAL) which is the most power efficient adiabatic topology reported in recent literature. The basic building blocks of the proposed GOTFET Adiabatic Logic (GOTAL) circuits are the innovative Complementary GOTFETs (CGOT) which have twice the on state currents Ion and one order lower off state currents Ioff than the corresponding MOSFETs having same width at the same technology node. In addition to the novel devices, the novelty in the proposed design is the usage of specially engineered low threshold voltage Vt GOTFETs for minimizing non-adiabatic losses and completely avoiding the unnecessary complexity involving the generation of discharge pulse in the resetting clock circuit. Adiabatic inverter, NAND and NOR gates implemented using the proposed GOTAL circuits consume up to two orders (97%) lower power than the corresponding conventional static CMOS circuits at the same frequencies of operation under the same capacitive loads. Although adiabatic circuits are usually designed for low frequency operation, GOTAL circuits may also be used at higher frequencies owing to the improved frequency response of the CGOT devices.
Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology
(Springer, 2019-02) Vidhyadharan, Sanjay
This paper presents the circuit performance of an optimized TFET device whose performance is not only better than most of the TFET devices reported in current literature, but exceeds the performance of state-of-the-art industry-standard 45 nm CMOS technology. Novel TFET structures have been proposed whose ON current (Ion) matches with that of the MOSFETs, while maintaining the OFF current (Ioff) at least 3 orders of magnitude lower than the MOSFETs with the same width and at the same technology node. The key performance metrics of the optimised TFET-based circuits have been benchmarked with similar CMOS-based standard digital circuits like the simple inverter, 2 input NAND gate, 2 input NOR gate, 2 input XOR gate, 6 transistor SRAM and 3 stage inverter chain. The overall improvement in Power Delay Product (PDP) of the TFET-based circuits has been demonstrated to be more than 97% lesser than the corresponding CMOS circuits.
CNFET Based Ultra-Low-Power Schmitt Trigger SRAM for Internet of Things (IoT) Applications
(Springer, 2021-09) Vidhyadharan, Sanjay
This paper presents Carbon Nanotube FET (CNFET) based ultra-low-power Schmitt trigger SRAM designs which can operate at voltage levels as low as 200 mV, with high Static Noise Margins (STM) of 100–120 mV. The hysteresis in the STM curve of the CNFET Schmitt SRAM has been achieved through proper adjustment of the threshold voltage Vth of the different CNFETs used to implement the SRAM. The Vth of the CNFET can be set to the required level by selecting the appropriate chiral vectors of the CNFET. The CNFET based SRAM consumes merely 3.2 pW of power as compared to 19.5 pW of power required by the same SRAM implemented with MOSFET devices. The CNFET SRAM also has an average propagation delay of 31 ps, which is significantly lower than the delay of 250 ns experienced in CMOS-based SRAM. A simplified multi-Vth 6T CNFET SRAM design is also proposed, which consumes merely 0.1 pW of power, thus enabling a 99% reduction in total power consumption in contrast to the conventional CMOS SRAM design. The device characteristics of the CNFET has been benchmarked with 45 nm CMOS devices. The improvement in the performance of the CNFET based SRAMs can be attributed to the 10 times higher ION:IOFF ratio and 18 times higher ION:CGG ratio of the CNFET as compared to the MOSFETs.
CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder
(Springer, 2021-02) Vidhyadharan, Sanjay
This paper proposes a carbon nanotube FET (CNFET)-based ultra-low-power dual-VDD ternary half adder (HA) circuit. The proposed design utilizes both the available ternary power supply voltages (VDD & VDD/2) and prevents direct path between the power supplies and ground, thus significantly reducing the power dissipation as compared to the conventional designs. The performance of the proposed CNFET dual-VDD HA has been compared with the same circuit implemented with 45 nm MOSFETs and also with other CNFET-based state-of-the-art HA designs proposed in the literature. The proposed HA consumes merely 86 nW of power which is significantly lesser (66–90% lower) than the power required by other ternary HA designs, and also exhibits 69–91% lower delays. The overall PDP of the proposed HA circuit is merely 4–11% of the PDP of corresponding CMOS ternary HA and other benchmarked CNFET HA designs.
An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices
(IEEE, 2019) Vidhyadharan, Sanjay
Recent studies have indicated that multilogic circuits in VLSI design helps in reducing the transistor count of circuits and increases the data transfer rate significantly. This paper presents an efficient design methodology for the implementation of a two bit ternary output Flash Analog to Digital Converter (ADC) utilizing Tunnel Field Effect Transistors (TFETs). Optimized SiGe TFET structures which have ON currents more than twice while OFF currents at least an order of magnitude lower than the standard 45 nm MOSFETs have been developed. These devices form the basic active elements for the proposed ADC. A new complementary TFET (CTFET) based comparator design is also proposed in the paper which has delays and power consumption lesser than the conventional CMOS based comparator design. An efficient methodology for directly designing logical functions with TFET devices, obtaining 2 bit ternary ADC output with a resolution of 50 mV and input quantized to 9 levels is illustrated in this paper. The proposed CTFET based ADC needs only 48 transistors to encode the comparator outputs to the required 2 bit ternary output which is significantly lower than the transistor count of 70 needed for the 2 bit ternary flash ADC designs available in literature. The performance of the CTFET based ternary ADC has been benchmarked with the same ADC circuit implemented with 45 nm CMOS technology. It has been demonstrated that the CTFET based ADC not only has delays much lesser than the corresponding CMOS based ADC but also consumes significantly lesser power and the overall decrease in Power Delay Product (PDP) has been shown to be 99.7%.
An Efficient Ultra-Low-Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices
(IEEE, 2021-01) Vidhyadharan, Sanjay
This paper presents a novel ultra-low power yet high-performance device and circuit design paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs (GOTFETs) and Carbon Nanotube FETs (CNFETs). One of the distinguishing novelty reported in this work is the introduction of an innovative GOTFET device, which exhibits more than double the on-currents I on and less than 1/10 th the off-currents I off of equivalent, equally-sized mosfets at the same technology node. Most of the ternary logic designs reported earlier in the literature encode ternary bits into binary for combinational functionality and then use an Encoder to get back ternary output. Unlike the earlier designs, this paper presents a novel and significantly more efficient approach of directly designing ternary logical functions with Low V t Transistors (LVT) and High V t Transistors (HVT) using CNFET and GOTFET technologies. The new approach simplifies the design and reduces the required transistor count & interconnects, thereby reducing the delays and power consumption. The proposed Ternary Half Adder (THA) circuit, designed using CMOS, enables a 52% reduction in transistor count compared to the conventional CMOS designs available in the literature. The THA implemented with CNFET exhibits 27 ps (87% lower delay than similar CMOS design and consumes 2.4 μW power (11% lower than CMOS). On the other hand, CGOT THA exhibits 101 ps (51% lower delay than similar CMOS design) and consumes merely 1.26 μW power (53% lower than CMOS, in ultra-low power regime). The overall decrease in the Power Delay Products (PDPs) are 88% and 77%, respectively, in the proposed CNFET and CGOT THA circuits compared to the CMOS THA.
Fast and Low-Power CMOS and CNFET based Hysteresis Voltage Comparator
(Taylor & Francis, 2023-01) Vidhyadharan, Sanjay
This paper presents CMOS and CNFET based hysteresis voltage comparators for low-voltage applications. The proposed CMOS and CNFET hysteresis comparators require merely 1.6 and 0.26 µW of power, respectively, which is less than one tenth of the power dissipated by the other advanced hysteresis comparators designs available in literature. The propagation delay observed in the proposed CMOS and CNFET hysteresis comparators are 162 and 47 ps, respectively, which is almost half the delay exhibited by the other hysteresis comparators. Overall, a 93–99% reduction in Power Delay Product (PDP) can be achieved. Furthermore, the proposed design requires only nine transistors compared to the 11–17 transistor requirement in conventional hysteresis comparators, thus saving up to 47% of chip area.
Gate-Overlap Tunnel Field-Effect Transistors (GOTFETs) for Ultra-Low-Voltage and Ultra-Low-Power VLSI Applications
(CRC, 2021) Vidhyadharan, Sanjay
The advancement in complementary metal oxide semiconductor (CMOS) technology during the last few decades has enabled scaling down of the metal oxide semiconductor field-effect transistor (MOSFET) feature size to below the 100 nano meter (nm) range. The power supply voltage across the devices must be reduced proportionately with the reduction in feature size to maintain the electric fields inside the device within junction breakdown limits. The gate overlaps the source completely, while it is terminated 22 nm short of the channel-drain junction. The gate overlaps the source completely, while it is terminated 22 nm short of the channel-drain junction. Jitter is the variation of the clock edge from its ideal instance. Clock jitter is usually caused by the clock generating circuit, noise, power supply fluctuations, and interference from adjacent components.
Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications
(Emerald, 2021-03) Vidhyadharan, Sanjay
Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels.
Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node
(Springer, 2020-01) Vidhyadharan, Sanjay
In this paper, four different types of gate-overlap tunnel FET (GOTFET) devices are proposed for ultra-low power applications: (1) generic GOTFETs for digital logic, (2) low- and high-threshold (LVT and HVT) GOTFETs for ternary logic, (3) multi-threshold GOTFETs giving both LVT and HVT characteristics by simply altering their terminal connections and (4) line-tunneling-based GOTFETs for analog applications. The most interesting feature of the proposed GOTFET is that in the same device structure, just by changing the material and doping parameters of the device, we can get the optimal performance for different applications. Each of these GOTFET structures have been optimized such that their characteristics are superior than equally sized 45-nm MOSFETs. Device optimization has been carried out by studying the impact of changes in various device parameters on performance. GOTFET characteristics were simulated using industry-standard synopsys® TCAD tools, while the benchmarking with an equivalent CMOS technology was carried out using the standard 45-nm CMOS library in industry-standard cadence® EDA tool. Proposed GOTFETs have minimum on-state currents Ion at least twice (Ion,GOT≥2Ion,MOS), with maximum off-state currents Ioff remaining at least an order of magnitude lower (Ioff,GOT≤0.1Ioff,MOS), than the corresponding equally sized MOSFETs at the same 45-nm technology node. Circuit analysis and designs are beyond the scope of this paper; however, the innovative GOTFETs proposed in this paper will serve as the basic active devices in digital, ternary logic and analog applications yielding circuit performance far superior to the state-of-the-art designs at the same technology node, as indicated in our previous reports.
An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger
(Elsevier, 2020-10) Vidhyadharan, Sanjay
This paper introduces an innovative Gate-Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield around double the on current Ion, while the off current Ioff remains around an order lower, than that of an analogous equally-sized MOSFET at the same technology node. Higher Ion: Ioff ratio and steeper sub-threshold slope of the proposed GOTFETs make them ideal candidates for ultra-low voltage applications like Schmitt trigger circuits. Considering the superior performance of the proposed GOTFET devices, simply replacing the MOSFETs with the proposed GOTFETs in conventional Schmitt trigger circuit significantly reduces the delays and static power consumption of the circuit as expected. At 0.4 V power supply voltage, there is 91.7% improvement in Power Delay Product (PDP) for Complementary GOTFET (CGOT) based conventional Schmitt trigger as compared to CMOS conventional Schmitt trigger for the same hysteresis width of 120 mV. In order to further minimize the dynamic power, a novel CGOT regenerative-latch Schmitt trigger design has also been presented in this paper for the first time, which further reduces the total (static + dynamic) power consumption and delays of the conventional Schmitt trigger circuit. The overall PDP in the proposed CGOT regenerative-latch based Schmitt trigger has been demonstrated to be merely 1.9% of (98.1% lower than) the PDP in corresponding CMOS conventional design.
Memristor–CMOS hybrid ultra-low-power high-speed multivibrators
(Springer, 2021-05) Vidhyadharan, Sanjay
Memristor–CMOS (MCM) technology enables fabrication of thin film memristors over the conventional CMOS devices and has the potential to significantly reduce the silicon-area and propagation delays in VLSI chips. The memristor not only has an extremely very useful characteristic of non-volatile memory, but also has the advantage of significantly lesser ON resistance Ron and lesser undesired parasitic capacitance as compared to MOSFETs. Innovative MCM hybrid re-configurable circuits can outperform conventional CMOS-only design and hence are being considered as an important device for future digital VLSI applications. This paper presents applications of TiO2−x–TiO2 memristor for digital multivibrator circuits at 45 nm CMOS technology node. The threshold adaptive memristor SPICE model has been used for design and performance-benchmarking of the proposed MCM multivibrators in circuit simulator (cadence®) at 45 nm technology node. The proposed new MCM mono-stable vibrator has a delay of merely 16 ps (98% lower delay than similar CMOS design) and requires a 45% lesser silicon area. Similarly, the proposed new MCM bi-stable vibrator has a delay of merely 5 ps (87% lower delay than similar CMOS design) and requires a 25% lesser silicon area. Moreover, the proposed MCM mono-stable and bi-stable multivibrators consume merely 0.1 μW and 0.5 μW of power, respectively, as compared to the 0.47 μW and 0.98 μW power required by corresponding CMOS-only multi-vibrators. The overall decrease in power delay product is 99% and 94%, respectively, in the proposed MCM mono-stable and bi-stable multivibrators as compared to the corresponding conventional CMOS-only multivibrators.
Mux Based Ultra-Low-Power Ternary Adders and Multiplier implemented with CNFET and 45 nm MOSFETs
(Taylor & Francis, 2021-04) Vidhyadharan, Sanjay
This paper presents improved multiplexer-based ultra-low-power ternary Half Adder (HA), ternary Full Adder (FA), and ternary 1-bit multiplier designs. The proposed circuits consume 61–91% lesser power and can be implemented with 10–40% lesser number of transistors, as compared to the other corresponding circuits available in the literature. The reduction in power and transistor count has been achieved through improved multiplexer designs and judicious use of pass transistor logic. CNFETs have low gate capacitance and hence are ideal devices for ultra-low-power VLSI applications; however, CMOS technology is presently the most preferred technology, because of the easy and low-cost fabrication option made available by the well-established CMOS fabrication labs. Keeping this in view, the proposed mux-based ternary half adder has been designed with both 45 nm MOSFETs and CNFETs. The performance of the proposed HA design has been benchmarked with other CNFET HA reported in the literature. The proposed mux-based CNFET ternary HA, FA and 1-bit multiplier have 10–30% lesser propagation delays than the other designs available in the literature. The reduction in the Power Delay Product (PDP) is 85–99% in the proposed mux-based CNFET ternary circuits as compared to the other benchmarked designs.
A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications
(Springer, 2019-06) Vidhyadharan, Sanjay
This paper introduces an innovative Gate Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield double the on current Ion, while the off current Ioff remains an order lower than the analogous MOSFET having same width at the same technology node. A conventional Dynamic Comparator designed using the proposed Complementary GOTFET (CGOT) paradigm exhibits 93 ps (25%) lower delay than similar CMOS designs and consumes merely 1.11 pW (99% lower than CMOS) of static power. The overall power delay product (PDP) in the CGOT comparator design has been shown to be only 0.5% of the PDP of a conventional CMOS comparator. Although the advantages of higher Ion are manifold, however, it increases dynamic power as well. So this paper goes beyond device-level improvisation and proposes for the first time, a novel improved comparator circuit designed using the CGOT paradigm which further reduces the total power by an additional 44.5%.
Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC
(Elsevier, 2020-07) Vidhyadharan, Sanjay
This paper presents a highly efficient ternary flash ADC, designed using the innovative gate-overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have on-state currents Ion more than double, while the off-state currents Ioff remaining at least an order of magnitude lower than the corresponding values of the standard 45 nm CMOS technology with the same width. Replacing MOSFETs with the proposed GOTFETs significantly reduces the static power consumption and improves performance. However, the higher Ion increases the dynamic power as well. To minimize the dynamic power, we propose a novel complementary GOTFET (CGOT) based comparator design. In addition to the inherent advantages of the GOTFET technology, the proposed design further reduces the dynamic power, such that the final power delay product (PDP) is merely 6.3% of the PDP in conventional CMOS comparator design. In addition to the novelty related to the innovative GOTFET devices, there are at least two-fold circuit-level novelty reported in this work. Firstly, we propose a novel CGOT based comparator circuit design, which, in addition to the advantages of GOTFET, further reduces the dynamic power such that the PDP is less than 1/3rd of the original PDP of the conventional comparator designed with GOTFETs. Secondly, the proposed CGOT based ADC requires only 48 transistors to encode the comparator outputs into the 2-bit ternary output, which is 30% lower than the 70 transistors necessary for the 2-bit CMOS based ternary flash ADC designs reported earlier in the literature. We propose an efficient 2-bit ternary flash ADC with a resolution of 50 mV and input quantized to 9 levels. Subsequently, we benchmark the performance of the proposed CGOT ternary flash ADC with the same ADC circuit implemented using the standard 45 nm CMOS technology library, all corresponding devices having the same width. We demonstrate that in addition to the superior performance than the corresponding CMOS ADC, the proposed CGOT ADC design consumes significantly lower power. The overall PDP of the proposed CGOT ADC is merely 6.3% of the PDP in corresponding CMOS design.
Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications
(IEEE, 2019) Vidhyadharan, Sanjay
For the first time, innovative low (LVT) and high (HVT) threshold tunnel FET devices have been reported for ternary logic applications. Based on an iterative algorithm, the DG TFET structures have been optimized such that the TFET characteristics are better than the MOSFETs having same width at the standard 45 nm technology node. These devices are designed in such a way that the low and high threshold voltages are VTL = VDD/3 and VTH = 2VDD/3 respectively, with the ranges {0 to VDD/3}, {VDD/3 to 2VDD/3} & {2VDD/3 to VDD} representing the 3 logic states 0, 1 & 2 respectively. Device optimization has been carried out by studying the impact of changes in various device parameters on performance. Optimized TFET devices have been benchmarked with standard CMOS for the same circuit designed using same technology. TFET device characteristics were simulated using Synopsys TCAD tools and circuit performance benchmarking was carried out with the standard 45 nm CMOS library using cadence EDA tool. Proposed LVT & HVT TFETs have ON currents (ION) roughly twice and OFF currents (IOFF) at least an order of magnitude lower than the corresponding MOSFETs. The performance of the optimized TFET based NTI & PTI ternary logic cells have been benchmarked with analogous CMOS circuits at same technology node. The overall Power Delay Products (PDP) of the TFET based logic cells have been demonstrated to be around 99.9% lower than the corresponding CMOS based logic cells. The proposed LVT & HVT TFET based NTI and PTI cells will serve as the starting point for any ternary logic applications.
A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM
(Elsevier, 2021-05) Vidhyadharan, Sanjay
This paper presents a CNTFET based ultra-low-power ternary SRAM design which consumes merely 66 nW of power, achieving 84–98% reduction in power consumption as compared to the other CNTFET ternary SRAM designs reported in the literature. The 6-Transistor (6T) Standard Ternary Inverter (STI) cell or the 3T-STI cell form the basic building block of the conventional SRAM cells. These conventional STI designs have an undesirable direct path between VDD and ground during certain ternary input signals, resulting in higher power consumption. In this paper, a highly power-efficient 4T-STI based Ternary SRAM design is presented, which prevents a direct path between the power supply VDD and ground in all the possible ternary logic states. While CNTFET is preferred by many researchers around the world for low-power VLSI applications, CMOS technology is still widely used in the industry because of the availability of advanced CMOS manufacturing units. Therefore, the proposed ultra-low-power ternary SRAM design has been implemented with both 32 nm CNTFET and 45 nm CMOS devices. The performance of both the CNTFET and CMOS based ultra-low-power ternary SRAM circuits have been benchmarked with corresponding conventional SRAM circuits. The overall decrease in Power Delay Product (PDP) is 86–97% in the proposed ultra-low-power ternary 32 nm CNTFET SRAM circuit and 87–99% in the proposed 45 nm CMOS SRAM with respect to corresponding conventional ternary SRAM circuits.
A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder
(Taylor & Francis, 2020-03) Vidhyadharan, Sanjay
Recent researches have indicated that the gate-overlap tunnel FETs (GOTFETs) exhibit double the on-currentsIon and one-tenth the off-currents Ioff than the equally sized MOSFETs at the same technology node, making them ideal candidates for ultra-low-power VLSI applications. This paper presents a complementary GOTFET (CGOT) based dynamic full adder (DFA), which consumes significantly lower power than conventional CMOS DFAs and operates at double the speed of CMOS DFAs. A conventional DFA designed using GOTFETs instead of MOSFETs exhibits 100 ps (40%) lower & 50 ps (30%) lower delays than CMOS DFA. Furthermore, the CGOT DFA consumes merely 2.6 pW of static power, which is 99% (2 orders) lower than the corresponding CMOS DFA ., Ion, . This paper proposes a novel improved DFA circuit design, which mitigates the dynamic power by eliminating redundant switching activity within the DFA circuit, . The proposed modified DFA topology reduces the total power consumption by 25% than the conventional DFA designs at 50% switching activity. The overall power delay product (PDP) reduces to merely 0.9% of the standard CMOS designs. The total power consumption reduces even further with decreasing switching activity, and the improved CGOT DFA consumes 31% lower total power (at 25% switching activity).
Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology
(Springer, 2019-02) Vidhyadharan, Sanjay
In this work, the structure of a TFET device has been engineered such that it is not only better than most of the TFETs reported in literature, it’s performance is even better than the MOSFETs of the standard 45 nm CMOS technology. The device-level optimization has been discussed, in which, starting with a simple double-gate fully depleted TFET structure, the gradual improvement in device performance has been demonstrated such that the final ON current is comparable to that of the MOSFETs, while the OFF current remains at least three orders of magnitude lesser than the MOSFETs at the same 45 nm technology node. Optimization of the device structure has been carried out by studying the impact of various asymmetries in the device structure. This work is intentionally restricted only to the asymmetries which can be incorporated without any change in the standard process technology.
Suppression of Ambipolar Behavior and Simultaneous Improvement in RF Performance of Gate-Overlap Tunnel Field Effect Transistor (GOTFET) Devices
(Springer, 2020-07) Vidhyadharan, Sanjay
This paper investigates a method to suppress the ambipolar current Iamb effectively, enhance the device performance with higher on current Ion, lower off current Ioff, lower inverse subthreshold slope SS and simultaneously improve the RF performance. Starting with a conventional double-gate TFET structure, the device optimization reported in this work has led to the gradual improvement in device performance in terms of higher Ion, lower Ioff, higher Ion/Ioff ratio and lower SS. The RF parameters of the optimized GOTFET, such as the mutual transconductance gm, gate-to-drain CGD, and gate-to-source CGS capacitances and unity-gain cut-off frequency fT are analyzed. We have optimized the tunnel FET device using the industry-standard synopsys® TCAD tools by studying the impact of various device parameters and dimensions on performance. We demonstrated that at high negative voltages, the proposed nGOTFET would completely suppress the ambipolar behavior of the device without deteriorating the device performance. We have compared the ambipolar current Iamb, Ioff, Ion, SS with 45 nm technology MOSFET and the TFETs reported earlier in literature. For the first time, we have proposed a GOTFET which completely suppresses the ambipolar current at high negative biases, without compromising the high Ion (1.04 mA/μ m) and low Ioff (0.27 pA/μ m) and low SS (32 mV/dec) at room temperature.