Department of Electrical and Electronics Engineering

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Start date: 2000Subject: search.filters.subject.Electronics Engineering

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    Design and Development of Performance Enhancement Techniques in Optical WDM Networks
    (BITS, Pilani, 2013-10) Shekhawat, Virendra Singh
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    Design, Simulation and Analysis of RF-MEMS Switches for Reconfigurable Antennas
    (BITS, Pilani, 2014-08) Sharma, Ashish Kumar
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    Design and Analysis of Soft-Switching Inverter for UPS Application
    (BITS, Pilani, 2008) Kumar, Rajneesh
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    Development of Novel Techniques for Fetal ECG Extraction in Early Pregnancy
    (BITS Pilani, 2010) Swarnalatha, R
    Congenital heart defects are among the most common birth defects and the leading newlinecause of birth defect-related deaths. Most cardiac defects have some manifestation in the newlinemorphology of cardiac electrical signals. The non invasive study of fetal cardiac signals can newlineprovide an effective means of monitoring the well-being of the fetal heart. This may be used newlinefor the early detection of cardiac abnormalities. The electrocardiogram (ECG) signal is the newlinegraphical recording of the electrical potential generated in association with heart activity. It is newlineone of the physiological signals commonly used in clinical aspects. As in adults, the wellbeing newlineand the status of the fetus can be assessed from a fetal electrocardiogram (FECG) newlinesignal. newlineNon invasive techniques of fetal monitoring are Doppler ultrasound, fetal newlineelectrocardiography and fetal magneto cardiography. Among these methods the most newlinecommonly used is Doppler ultrasound because it is simple to use and cheap. However this newlinemethod produces an averaged heart rate and therefore cannot give beat to beat variability. newlineFetal electrocardiogram offers the advantage of monitoring beat to beat variability. There are newlinemany technical problems with non invasive extraction of FECG. The FECG signal is newlinecorrupted by different sources of interferences such as maternal electrocardiogram (MECG) newlinematernal electromyogram (MEMG), 50 Hz power line interference and base line wander. newlineThe low amplitude of the signals, the different types of noise and overlapping frequencies of newlinemother and fetal ECG make the extraction of FECG a difficult task. newlineExtraction and analysis of the fetal ECG signal are the primary objectives of newlineelectronic fetal monitoring. In extracting the fetal ECG signal, the digital signal processing newlinetechniques have played a significant role. The primary assumption is that the abdominal ECG newlineiv newlinesignal (AECG) is a non linear combination of the maternal ECG, fetal ECG signal and other newlineinterference signal.
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    A Comparative Study of High Performance CMOS Multipliers Barrel Shifters and Modeling of NBTI Degradation in Nanometer Scale Digital VLSI Circuits
    (BITS Pilani, 2009) Asati, Abhijit Rameshwar
    The objective of this thesis is to explore the design space of two specific data path newlineelements (viz multipliers and barrel shifters) of different bit width at architectural-level, newlineat logic design level, and at transistor size level to select proper architecture, logic design newlinestyle and physical device sizes; keeping in a view their effects on performance (circuit newlinedelay), average power consumption and core area. newlineThe multipliers and barrel shifters are the fundamental data path elements required in newlinehigh performance Standard Digital Signal Processors and ASIC Digital Signal newlineProcessors used for digital signal processing (DSP). Different multiplier and barrel newlineshifter architectures show trade-offs between propagation delay, average power newlineconsumption and transistor counts. In deep sub-micron technologies, the simple gatelevel newlineanalyses are inadequate to validate particular data path architectures. In this thesis newlinewe considered the effects of wiring parasitics and MOS parasitics in the assessment of newlinearchitecture. The selected word widths for different multiplier and barrel shifter newlinearchitectures are 4-bit, 8-bit, 12-bit and 16-bit; which dominate in DSP applications. newlineA schematic and physical library consisting of functional cells was defined for static newlineCMOS logic design style, transmission gate (TG) logic design styles, dual rail domino newlinelogic design style and true single phase clock (TSPC) logic design style. Versions of the newlinephysical libraries were developed using three different sizes of transistors. The layout assemblies for the 4-bit, 8-bit, 12-bit and 16-bit multiplier and barrel shifter circuits were carried out using these cell libraries using automatic place and route tool LEDIT (SPR) newlinefrom M/s Tanner Research Inc. The circuit delay and average power dissipation then newlineanalyzed for each implementation of the multiplier and barrel shifter circuit using the same logic design style but utilizing three different physical libraries differing in their transistor sizes as described above.