Department of Electrical and Electronics Engineering
Permanent URI for this collectionhttp://localhost:4000/handle/123456789/1844
Browse
Item A 7-cell, stackable, Li-ion battery monitoring and balancing system for electric and hybrid vehicles(BITS, Pilani, 2018) Vulligaddala, Veeresh babuItem Analysis and classification of vibroarthographic signal using nonstationary signal processing techniques(BITS, Pilani, 2018-03) Shehnaz, Nalband Saif DilavarItem Analysis and design of FFT processor architecture for OFDM applications(BITS, Pilani, 2018) Kumar, Ganjikunta ganeshItem Analysis and design of terahertz wireless communication Integrated with access, IoT, and cell free networks(BITS Pilani, Pilani Campus, 2024) Bhardwaj, PranayItem Analysis of Load Frequency Control of Multi-Area Power System with Fuzzy Logic Controller(BITS Pilani, 2007) Mathur, Hitesh DattItem Ant-Colony based energy efficient routing technique for wireless body area networks(BITS, Pilani, 2018) RakheeItem Architectures and Algorithms for Image and Video Processing using FPGA-based Platform(BITS Pilani, 2014-05) Pandey, Jai GopalItem Artificial intelligence enabled vehicular vision and service provisioning for advanced driver assistance systems (ADAS)(BITS PILANI, Pilani campus, 2024) Chougule, Amit UmeshItem Automatic leather species identification using digital microscopic image analysis(BITS PILANI, Goa campus, 2024) Varghese, AnjliItem Battery Monitoring using Source Side Excitation with Voltage Pulse Sequence(BITS, Pilani, 2018) Madhuri, BayyaItem Carbon nanomaterial based flexible pressure/strain sensors for wearable electronics(BITS Pilani, Pilani Campus, 2024-03) Baloda, SurajItem Carbon TiO2 Nanocomposites based Devices for Detection of Volatile Organic Compounds(BITS Pilani, 2021) Gakhar, TeenaItem Clock Synchronization in Satellite Terrestrial and IP Set top Box for Digital Television(BITS, Pilani, 2010-03-29) Jain, MonikaItem A Comparative Study of High Performance CMOS Multipliers Barrel Shifters and Modeling of NBTI Degradation in Nanometer Scale Digital VLSI Circuits(BITS Pilani, 2009) Asati, Abhijit RameshwarThe objective of this thesis is to explore the design space of two specific data path newlineelements (viz multipliers and barrel shifters) of different bit width at architectural-level, newlineat logic design level, and at transistor size level to select proper architecture, logic design newlinestyle and physical device sizes; keeping in a view their effects on performance (circuit newlinedelay), average power consumption and core area. newlineThe multipliers and barrel shifters are the fundamental data path elements required in newlinehigh performance Standard Digital Signal Processors and ASIC Digital Signal newlineProcessors used for digital signal processing (DSP). Different multiplier and barrel newlineshifter architectures show trade-offs between propagation delay, average power newlineconsumption and transistor counts. In deep sub-micron technologies, the simple gatelevel newlineanalyses are inadequate to validate particular data path architectures. In this thesis newlinewe considered the effects of wiring parasitics and MOS parasitics in the assessment of newlinearchitecture. The selected word widths for different multiplier and barrel shifter newlinearchitectures are 4-bit, 8-bit, 12-bit and 16-bit; which dominate in DSP applications. newlineA schematic and physical library consisting of functional cells was defined for static newlineCMOS logic design style, transmission gate (TG) logic design styles, dual rail domino newlinelogic design style and true single phase clock (TSPC) logic design style. Versions of the newlinephysical libraries were developed using three different sizes of transistors. The layout assemblies for the 4-bit, 8-bit, 12-bit and 16-bit multiplier and barrel shifter circuits were carried out using these cell libraries using automatic place and route tool LEDIT (SPR) newlinefrom M/s Tanner Research Inc. The circuit delay and average power dissipation then newlineanalyzed for each implementation of the multiplier and barrel shifter circuit using the same logic design style but utilizing three different physical libraries differing in their transistor sizes as described above.Item Compiler assisted parallelization and optimization for multicore architecture(BITS, Pilani, 2014-01-08) Kiran, D CItem Compression and error robustness performance improvement of a scalable multi view video coding frame work(BITS, Pilani, 2016-12-02) Guruvareddiar, PalanivelItem Computational Intelligence Based Face Recognition(BITS, Pilani, 2015-08-18) Agarwal, VandanaItem Computational model predictions of acoustic and auditory changes for concurrent vowel identification(BITS Pilani, 2021) Harshavardhan, SItem Computer Vision based Intelligent Techniques for Hand Gesture Recognition(BITS, Pilani, 2012-03) Chaudhary, AnkitItem Computerization of students records at BITS for educational administration management and monitoring(BITS, Pilani, 1991-12) Mittal, Ravi Kant