BITS Faculty Publications

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    High Field Stressing Effects in JVD Nitride Capacitors
    (SPIE, 2001) Rao, V. Ramgopal
    The performance of Jet Vapour Deposited (JVD) Silicon Nitride devices under high field stressing is reported in this paper. Border traps were generated when n-substrate capacitors were stressed with negative gate voltages. Also, an increase in bulk positive charges as well as interface trap density was observed. These results indicate that stressing under negative gate voltages may cause long term reliability problems in Metal-Nitride-Semiconductor (MNS) devices'. Stressing with positive gate voltage, however, does not show any significant degradation.
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    NEXT Fabrication of Unipolar Graphene Field-Effect Transistors by Modifying Source and Drain Electrode Interfaces with Zinc Porphyrin
    (ACS, 2012) Rao, V. Ramgopal
    We report a unipolar operation in reduced graphene oxide (RGO) field-effect transistors (FETs) via modification of the source/drain (S/D) electrode interfaces with self-assembled monolayers (SAMs) of 5-(4-hydroxyphenyl)-10,15,20-tri-(p-tolyl) zinc(II) porphyrin (Zn(II)TTPOH) molecules. The dipolar Zn(II)TTPOH molecules at the RGO/platinum (Pt) S/D interface results in an increase of the electron injection barrier and a reduction of the hole-injection barrier. Using dipole measurements from Kelvin probe force microscopy and highest occupied molecular orbital–lowest unoccupied molecular orbital (HOMO–LUMO) calculations from cyclic voltammetry, the electron and hole injection barriers were calculated to be 2.2 and 0.11 eV, respectively, indicating a higher barrier for electrons, compared to that of holes. A reduced gate modulation in the electron accumulation regime in RGO devices with SAM shows that unipolar RGO FETs can be attained using a low-cost, solution-processable fabrication technique.