BITS Faculty Publications
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Item A comprehensive survey on data converters for IOT applications: scope, issues, and future directions(IEEE, 2025-03) Gupta, Anu; Shekhar, Chandra; Chamola, VinayData converters significantly contribute to efficient and accurate data processing in Internet of Things (IoT) systems. As IoT expands into agriculture, industrial automation, and healthcare (AIH), precise and low-power data conversion has become crucial to support longer battery life and reliable performance in IoT devices. Efficient data converters are key to reducing energy use, especially in components like comparator circuits, which consume significant energy in successive approximation register analog-to-digital converters (SAR ADCs). This survey provides an in-depth review of recent developments in low-power data converter design, examining techniques that help reduce power consumption at various stages. It emphasizes advancements, such as energy scaling, dynamic voltage references, and architectural optimizations that enhance efficiency without compromising performance. A specific analysis of emerging technology trends, such as the application of machine learning in data converter design, is explored to stimulate further innovation. Machine learning (ML)-based optimization, including adaptive calibration, noise reduction, and real-time performance optimization, presents new opportunities for enhancing efficiency and accuracy while addressing critical design constraints in IoT applications. While quantum encryption offers promising advancements in securing IoT data transmission, a broader security perspective beyond encryption is necessary, including concerns, such as attack detection and data integrity, ensuring the robustness of IoT systems. This review also examines latency, signal integrity, and accuracy issues, offering a roadmap for next-generation converter designs and reducing power consumption in data converters, which are fundamental to enhancing the performance and lifespan of IoT devices.Item A 12.11 mW, 99 pJ/Conv.-Step SAR ADC with Optimal Power Efficiency for IoT(IEEE, 2024-12) Gupta, Anu; Shekhar, ChandraThis brief presents a capacitive charge scaling DAC architecture with a two-phase non-overlapping clocking scheme to make an energy-efficient Successive Approximation Register (SAR) data converter for Internet-of-Things (IoT) applications. The proposed architecture comprises a Track & Hold (T/H), a Modified Strong Arm Latch comparator (MSAL), a SAR Control logic, and a digital-to-analog (D/A) converter. The proposed work is simulated using Cadence Virtuoso in TSMC 180 nm and achieves a minimum sampling rate of 1 MS/s and power consumption of 12.11 mW. To address the effects of process variations and mismatches on ADC performance, this paper conducts a thorough 500-point Monte Carlo (MC) simulation of the proposed SAR ADC circuit. The measured results show a Signal-to-Noise Ratio (SNR) of 47.81 dB, a Spurious-Free Dynamic Range (SFDR) of 54.32 dB, and ENOB of 7.65 Bits.Item Design & Analysis of Performance-efficient Comparator for IoT Application(IEEE, 2022) Shekhar, Chandra; Gupta, AnuThe regenerative latch comparator prototype for high-speed up to 1 Giga Hertz analog-to-digital conversion is shown in this article. Cascading structure of different modules makes the proposed comparator a suitable choice for various converters like SAR, Pipelined, Flash, etc. The proposed comparator achieves efficiency in terms of propagation latency, power consumption, and area as compared to the present state of the art mentioned in this work. Additionally, it uses the cadence schematic editor tool to illustrate how the performance of a comparator changes depending on its common-mode voltage (Vcm) and input (Vid) on TSMC 180 nm CMOS technology.Item Comparative Analysis of Phase/Frequency Detector in a Complete PLL System(IEEE, 2023) Gupta, Anu; Shekhar, ChandraIn many integrated radio frequency (RF) transceivers, the phase-locked loop (PLL) serves as a frequency synthesizer. This work goes to test various different phase/frequency detector blocks with a standard charge pump and Voltage controlled oscillator design. These include the comparison of different phase-frequency detectors (PFD) based upon D-flipflops, latches (Latch PFD) & pass transistors (PTPFD) to the more complex Pre-charged PFD. The best results of the PFDs in the PLL system in order are Pre-charge PFD, PT-PFD, Latch PFD and D-flipflop PFD. A charge pump PLL (CPLL) with a frequency range of [80 MHz -800 MHz] is simulated using Cadence Virtuoso (Spectre) at 180nm technology (scl\_pdk) with 1.8 V supply voltage. The phase noise of the VCO is less than -50dBc/Hz at 10MHz and is closer to 110dBc/Hz at 1GHz.Item Comparative Analysis of D/A Converter Architectures for SAR ADC(IEEE, 2024-02) Gupta, Anu; Shekhar, ChandraThis study gives an in-depth analysis of the architectures utilized in the analog-to-digital conversion process. The paper encompasses the design, performance, and suitability of the binary-weighted (charge distribution), R-2R ladder, and C-2C Digital-to-Analog (D/A) Converter architectures. This paper's discussed D/A converter architectures are simulated through the cadence tool using 180 nm CMOS technology. Based on comparative performance analysis, the C-2C D/A converter gives optimum results in terms of power, speed, DNL, INL, and settling time while maintaining its resolution. C-2C D/A converter reported a 63.15% improvement in power consumption compared to R-2R DAC, DNL, and INL errors below 0.01 LSB.Item Design and implementation of successive approximation register data converter(AIP, 2024) Gupta, Anu; Chaturvedi, Nitin; Shekhar, ChandraAnalog-to-Digital Converters (ADCs) serve as crucial interfaces between the analog and digital domains, facilitating the transformation of analog signals into digital representations. Data processing in the digital domain presents distinct performance advantages over the analog domain in particular aspects. To facilitate the reverse conversion of processed digital signals back into the real-world signal domain, Charge Redistribution Digital-to-Analog Converters (DACs) are employed. DACs also play a pivotal role as significant components in specific ADC architectures, such as the Successive Approximation Register (SAR) Analog-to-Digital (A/D) Converter. Moreover, a Strong-Arm Latch Comparator has been utilized to compare the input analog voltage with the output voltage of the DAC. This paper primarily focuses on the implementation and thorough analysis of the SAR-ADC. The study includes calculatinganalog voltages’ precise range and corresponding digital outputs. The maximum Differential Non-Linearity (DNL) error, offset error, and full-scale error for this specific SAR-ADC have been measured and found to be 0.28*LSB, 0.2*LSB, and 0.22*LSB, respectively. The results presented in this paper provide valuable insights into the performance and accuracy of the SAR-ADC, paving the way for further advancements and applications in the domain of A/D conversion.Item A Novel Bootstrapped CMOS Switch with Minimized Sampling and Holding Error Using Sampling Window Error Analysis(World Scientific, 2024) Gupta, Anu; Shekhar, ChandraThis study proposes a novel 6-transistor bootstrapped switch with minimized sampling and holding error obtained through sampling window error analysis for SAR ADC design. The proposed switch design strategically mitigates channel charge injection and minimizes the input signal dependency of on-resistance by optimizing its sizing parameters. To counteract channel charge effects, dummy NMOS and PMOS components are judiciously employed, culminating in a substantial improvement in the effective number of bits (ENOB). The complete analysis of the proposed circuit is done using the Cadence Virtuoso SCL 0.18 μm CMOS process. For a 51.514 kHz sinusoidal 1 V peak-to-peak differential input signal with a 1 MSPs clock speed, the proposed circuit achieves 2.0141 mV maximum sampling window error, 0.131 μW power consumption, 84.67 dB signal-to-noise ratio (SNR), 84.67 signal-to-noise and distortion (SINAD) ratio and 86.02 dB spurious-free dynamic range (SFDR), which produces 13.77 bits ENOB. For the impacts of process variations and mismatch on switch performance, a comprehensive 500-point Monte Carlo (MC) simulation of the proposed bootstrap switch is conducted in this study. Post-layout results show that the proposed circuit is suitable for IoT applications.Item A Three-Stage Dynamic Comparator for SAR ADC Optimized for Reduced Kickback Noise and Ultra-Low Delay(World Scientific, 2024) Gupta, Anu; Shekhar, ChandraThis paper presents a novel footless single clock-phase three-stage comparator with internally generated regenerative voltage signals for low kickback noise and high speed. The preamplifier and clocked latch topology of dynamic comparators are considered in this brief. The proposed design has been compared by analyzing and optimizing three state-of-the-art comparator designs: Modified StrongARM, Miyahara’s and Three-Stage. These designs are simulated using the 40nm CMOS technology process. The area of the proposed comparator is 28.025μm2. When simulated in the SPICE-based simulator HSPICE, under typical performance conditions of 0.9V supply voltage, 25∘C, 1 GHz operational frequency, typical process corner (tt), and 1mV differential voltage, the proposed comparator produces the best post-layout results, with a minimum delay of 59.9ps from meta-stability analysis, energy per comparison of 0.175pJ/comparison and a kickback noise of 44.55 μA. The proposed design also shows a significant improvement in the measured performance parameters over the other state-of-the-art dynamic comparators that have been discussed in this brief. The obtained results show that the proposed comparator is appropriate for 12-bit Successive Approximation Resister Analog-to-Digital Converters (SAR-ADCs) in IoT applications.Item Design and Analysis of Modified Strong Arm Latch Comparator with Reduced Kickback Noise(Springer, 2024-10) Gupta, Anu; Shekhar, Chandra; Chaturvedi, NitinThis research paper introduces three techniques to reduce kickback noise in the Strong Arm Latch Comparator (SAL). The first technique focuses on utilizing high clock power and generating two clocks with different duty cycles. While initially addressing the issue by applying a single clock to the kickback-reducing circuit, the reduction of kickback noise did not meet the desired level. To overcome this limitation, a new design is proposed, incorporating a delay in the programmability of the kickback-reducing circuit, which effectively eliminates the need for kickback and clock requirements. A comparative study is conducted, evaluating all the designs, including the proposed design, based on power, delay, and analysis of various types of noise. Results show that the proposed technique outperforms other kickback-reducing designs in terms of propagation latency, power consumption, and kickback currents. Additionally, the impact of a comparator’s common-mode voltage (Vcm) on its performance in TSMC 180 nm CMOS technology is demonstrated using the Cadence Schematic Editor tool.Item Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load(IEEE, 2009) Asati, Abhijit; Shekhar, ChandraThe PMOS/NMOS width ratio (ß) and W/L ratio of NMOS device is an important ratio in the design of digital logic cells using conventional CMOS logic design style. In this paper we propose a simulation-based method applied to CMOS inverter to accurately estimate an optimum W/L ratio of NMOS device and PMOS/NMOS width ratio when fanout loading of 1, 4 and 8 cells of similar type are present. The appropriate selection of W/L ratio of NMOS device and PMOS/NMOS width ratio makes the digital design faster and reduces the power consumption.