BITS Faculty Publications

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    Investigation into gate dielectric material using different optimization techniques in carbon nanotube field effect transistors
    (Journal of Micromechanics and Microengineering, 2019) Navneet, Gupta
    This paper presents an analysis of gate dielectric materials using different optimization techniques for carbon nanotube field effect transistors. The selection of the best gate dielectric is done using multi-criteria decision-making methods, i.e. Ashby's, TOPSIS (technique for order preference by similarity to ideal solution) and VIKOR (VlseKriterijumska Optimizacija I Kompromisno Resenje in Serbian). The selection criteria for the best dielectric material are based on various material indices which include relative dielectric constant (εr), energy band gap (Eg), conduction band offset and coefficient of thermal expansion. This analysis concludes that lanthanum oxide (La2O3) is the most promising dielectric material, followed by HfO2. All these material selection methodologies converge on the same results. This result is compared with the experimental findings, and the close match between analytical and experimental results confirms the validity of this study.
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    Simulations of the CNFETs using different high-k gate dielectrics
    (IAES, 2020) Gupta, Navneet
    In this paper we presented the analysis of Carbon Nanotube Field Effect Transistors (CNFETs) using various high-k gate dielectric materials. The objective of this work was to choose the best possible material for gate dielectric. This paper also presented the study on the effect of thickness of gate dielectric on the performance of the device. For the analysis (19, 0) CNT was considered because the diameter of (19, 0) CNT is 1.49nm and the CNFETs have been fabricated with the CNT diameter of ~1.5nm. It has been observed that La2O3 is the best gate dielectric material followed by HfO2 and ZrO2. It was also observed that as thickness of gate dielectric material reduces, drain current of CNFET increases. The outcomes of this study matches with the analytical results and hence confirm the results
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    A Compact Model of Gate Capacitance in Ballistic Gate-All-Around Carbon Nanotube Field Effect Transistors
    (MERC, 2021) Gupta, Navneet
    This paper presents a one-dimensional analytical model for calculating gate capacitance in Gate-All-Around Carbon Nanotube Field Effect Transistor (GAA-CNFET) using electrostatic approach. The proposed model is inspired by the fact that quantum capacitance appears for the Carbon Nanotube (CNT) which has a low density of states. The gate capacitance is a series combination of dielectric capacitance and quantum capacitance. The model so obtained depends on the density of states (DOS), surface potential of CNT, gate voltage and diameter of CNT. The quantum capacitance obtained using developed analytical model is 2.84 pF/cm for (19, 0) CNT, which is very close to the reported value 2.54 pF/cm. While, the gate capacitance comes out to be 24.3×10-2 pF/cm. Further, the effects of dielectric thickness and diameter of CNT on the gate capacitance are also analysed. It was found that as we reduce the thickness of dielectric layer, the gate capacitance increases very marginally which provides better gate control upon the channel. The close match between the calculated and simulated results confirms the validity of the proposed model.