Optimization of sub 100 nm Γ-gate Si-MOSFETs for RF applications
| dc.contributor.author | Rao, V. Ramgopal | |
| dc.date.accessioned | 2023-10-30T09:20:53Z | |
| dc.date.available | 2023-10-30T09:20:53Z | |
| dc.date.issued | 2005-04 | |
| dc.description.abstract | This paper presents characterization and simulation studies on the RF performance of the Γ (Gamma) gate MOSFETs. The Γ-gate MOSFET offers the advantage of reduced gate resistance, a critical parameter in high frequency circuits. The aim of this study is to identify the optimum Γ-gate extension length from the gate and drain resistance point of view in aggressively scaled CMOS. | en_US |
| dc.identifier.uri | http://repository.ias.ac.in/79790/ | |
| dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12725 | |
| dc.language.iso | en | en_US |
| dc.subject | EEE | en_US |
| dc.subject | MOSFETs | en_US |
| dc.subject | CMOS technologies | en_US |
| dc.title | Optimization of sub 100 nm Γ-gate Si-MOSFETs for RF applications | en_US |
| dc.type | Article | en_US |
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