High Performance Binary Logarithmic and BCD Multiplier Architectures

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dc.contributor.authorAhmed, Syed Ershad
dc.date.accessioned2022-09-29T11:43:23Z
dc.date.available2022-09-29T11:43:23Z
dc.date.issued2017
dc.descriptionUnder Supervision: Srinivas, M. Ben_US
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/5179
dc.language.isoenen_US
dc.publisherBITS Pilanien_US
dc.subjectElectrical & Electronics Engineeringen_US
dc.subjectTechnologyen_US
dc.titleHigh Performance Binary Logarithmic and BCD Multiplier Architecturesen_US
dc.typeThesisen_US

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