A new physical insight and 3D device modeling of STI type denmos device failure under ESD conditions

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Date

2009

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IEEE

Abstract

We present experimental and simulation studies of STI type DeNMOS devices under ESD conditions. The impact of base-push-out, power dissipation because of space charge build-up and, regenerative NPN action, on the various phases of filamentation and the final thermal runaway is discussed. A modification of the device layout is proposed to achieve an improvement (~2X) in failure threshold (I T2 ).

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Keywords

EEE, Electrostatic discharge (ESD), Protection, CMOS technology, Space charge, CMOS process, Space technology, Power dissipation, Circuit simulation

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