A new physical insight and 3D device modeling of STI type denmos device failure under ESD conditions

dc.contributor.author	Rao, V. Ramgopal
dc.date.accessioned	2023-10-27T10:54:35Z
dc.date.available	2023-10-27T10:54:35Z
dc.date.issued	2009
dc.description.abstract	We present experimental and simulation studies of STI type DeNMOS devices under ESD conditions. The impact of base-push-out, power dissipation because of space charge build-up and, regenerative NPN action, on the various phases of filamentation and the final thermal runaway is discussed. A modification of the device layout is proposed to achieve an improvement (~2X) in failure threshold (I T2 ).	en_US
dc.identifier.uri	https://ieeexplore.ieee.org/document/5173327
dc.identifier.uri	http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12681
dc.language.iso	en	en_US
dc.publisher	IEEE	en_US
dc.subject	EEE	en_US
dc.subject	Electrostatic discharge (ESD)	en_US
dc.subject	Protection	en_US
dc.subject	CMOS technology	en_US
dc.subject	Space charge	en_US
dc.subject	CMOS process	en_US
dc.subject	Space technology	en_US
dc.subject	Power dissipation	en_US
dc.subject	Circuit simulation	en_US
dc.title	A new physical insight and 3D device modeling of STI type denmos device failure under ESD conditions	en_US
dc.type	Article	en_US

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