Characterization of interface and oxide traps in Ge pMOSFETs based on DCIV technique
| dc.contributor.author | Rao, V. Ramgopal | |
| dc.date.accessioned | 2023-11-03T08:59:35Z | |
| dc.date.available | 2023-11-03T08:59:35Z | |
| dc.date.issued | 2009-06 | |
| dc.description.abstract | The interface trap density of fresh TiN/TaN gated HfO 2 /SiO 2 /Si/epi-Ge pMOSFETs is measured using the DCIV technique. Its temperature dependence is also discussed here. We observe a polarity dependent DCIV peak shift. The bias temperature stress induced interface trapped charge and oxide trapped charge shifts are also systematically investigated in this work. | en_US |
| dc.identifier.uri | https://ieeexplore.ieee.org/document/5166133 | |
| dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12842 | |
| dc.language.iso | en | en_US |
| dc.publisher | IEEE | en_US |
| dc.subject | EEE | en_US |
| dc.subject | Ge pMOSFET | en_US |
| dc.subject | Interface trap | en_US |
| dc.subject | Oxide trap | en_US |
| dc.title | Characterization of interface and oxide traps in Ge pMOSFETs based on DCIV technique | en_US |
| dc.type | Article | en_US |
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