Browsing by Author "Rao, V. Ramgopal"

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1/f Noise in Drain and Gate Current of MOSFETs With High-k Gate Stacks Publisher: IEEE PDF
(IEEE, 2009-06) Rao, V. Ramgopal
In this paper, we investigate the quality of MOSFET gate stacks where high- k materials are implemented as gate dielectrics. We evaluate both drain- and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high- k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/ f noise point of view.
100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric
(IEEE, 1999) Rao, V. Ramgopal
Metal-nitride-semiconductor (MNS) FETs with channel lengths down to 100 nm with a novel jet vapor deposited (JVD) SiN insulator as gate dielectric are fabricated and characterized for their electrical performance. By employing the charge pumping technique, the SiN interface quality and its effect on the transistor performance are evaluated. We show that, compared to conventional SiO/sub 2/ MOSFETs, the SiN devices show lower gate leakage current, competitive drain current drive and transconductance, good interface quality, and reduced hot-carrier degradation.
3D TCAD based approach for the evaluation of nanoscale devices during ESD failure
(IEEE, 2010-11) Rao, V. Ramgopal
This paper demonstrates a 3D TCAD based approach towards the evaluation and pre-silicon development of nanoscale devices for advanced ESD protection concepts. Impact of various physical models and parameters on the accuracy of predicted ESD figures of merit are discussed. Moreover, various devices options, have been evaluated from 3D TCAD simulations.
A 8-resistor SU-8 accelerometer with reduced cross axis sensitivity
(IEEE, 2010) Rao, V. Ramgopal
The MEMS accelerometer has a high cross sensitivity due to proof mass being eccentric. This paper gives results for a SU-8 z-axis accelerometer that uses 8-resistor Wheatstone-bridge to reduce the x-axis and y-axis cross sensitivity by 2 orders of magnitude compared to the conventional 4-resistor Wheatstone-bridge arrangement.
Affinity cantilever sensors for cardiac diagnostics
(NISCAIR, 2007-04) Rao, V. Ramgopal
Cardiac problems are on the rise in the Indian sub-continent due to the changing life styles and food habits. Acute Myocardial Infraction (AMI) is becoming a major concern. In this paper, we report the development of affinity cantilever based sensors for the detection of AMI with optical and electrical readouts. We designed, simulated and fabricated these cantilevers with various micro fabricated materials such as silicon dioxide, silicon nitride and SU-8. Thin films such as silicon nitride and p-type polysilicon are deposited using hot wire CVD technique. For electrical detection, p-type polysilicon was used as a piezoresistive layer. The mechanical and electrical performance parameters of these cantilevers were investigated using Atomic Force Microscope (AFM) set-up. The top surface of these cantilevers was selectively immobilized with the antibodies. Following this, antibody specific antigens were allowed to react with the cantilever surface in the liquid cell of AFM set-up for the optical detection. For electrical signal detection, microcontroller based signal conditioning and digital readout circuit was developed.
Al-doped ZnO thin-film transistor embedded micro-cantilever as a piezoresistive sensor
(AIP, 2013-02) Rao, V. Ramgopal
In this work, an aluminium-doped zinc oxide (AZO) thin film transistor, embedded in a polymer micro-cantilever, is demonstrated for nano-mechanical sensing applications. This device senses the surface stress due to a change in the carrier mobility of the semi-conducting layer. Due to the low Young's modulus and high strain sensitivity of the AZO layer, this micro-cantilever shows a deflection sensitivity of 116 ppm per nanometer of deflection. Also, mechanical characterization of these devices shows that the resonance frequency is in the range of a few tens of kilohertz which is suitable for sensor applications.
Al-doped ZnO thin-film transistor embedded microcantilever as a piezoresistive sensor
(AIP, 2013) Rao, V. Ramgopal
In this work, an aluminium-doped zinc oxide (AZO) thin film transistor, embedded in a polymer micro-cantilever, is demonstrated for nano-mechanical sensing applications. This device senses the surface stress due to a change in the carrier mobility of the semi-conducting layer. Due to the low Young's modulus and high strain sensitivity of the AZO layer, this micro-cantilever shows a deflection sensitivity of 116 ppm per nanometer of deflection. Also, mechanical characterization of these devices shows that the resonance frequency is in the range of a few tens of kilohertz which is suitable for sensor applications.
Analog Circuit Performance Issues with Aggressively Scaled Gate Oxide CMOS Technologies
(IEEE, 2006) Rao, V. Ramgopal
MOS transistors with sub 100 nm channel lengths need a gate oxide thickness in the range of 1-2 nm to combat the short channel effects. However at these gate dielectric thicknesses, the gate current is no longer negligible. In this paper, we report the device analog behavior with extremely scaled oxides for integrating mixed signal circuits using the scaled digital CMOS technologies. We show the performance of common source amplifiers and current mirror circuits with these technologies. Our results also show that though thin oxides result in good voltage gains of amplifier circuits, the increased gate leakage degrades the performance of current mirror circuits. We also analyze the performance of different classes of current mirror circuits in the presence of gate leakage and provide broad guidelines for analog circuit design in the presence of gate leakage.
Analog Device and Circuit Performance Degradation under Substrate Enhanced Hot Carrier Stress Conditions
(IEEE, 2006) Rao, V. Ramgopal
In this paper, we investigate the influence of forward and reverse body bias stress on the hot carrier induced degradation of MOS analog performance parameters. The underlying physical mechanisms are identified with the help of experimental results, TCAD and Monte-Carlo simulations. We show that under forward body bias stress conditions, the auger recombination enhanced hot carrier injection (HCI) degrades the device and circuit performance considerably. Degradation in various analog circuits’ performance is quantified by considering the individual transistors under different stress conditions.
Analysis of dependence of short-channel effects in double-gate MOSFETs on channel thickness
(Elsevier, 2010-03) Rao, V. Ramgopal
A systematic study of the dependence of short-channel effects (SCEs) on the channel thickness (Tch) of double-gate MOSFETs revealed that there is a particular range of Tch in which SCEs are significantly degraded compared to those of conventional planar MOSFETs. This phenomenon was found to originate from the electric field penetrating the channel region from the drain due to the disappearance of a neutral region in the channel. This dependence of this phenomenon on device parameters such as the channel doping concentration (Nc), the equivalent oxide thickness (EOT) and the gate length (Lg) was examined. The degradation of SCEs due to an inappropriate Tch was found to become more significant as Nc and Lg are reduced.
Analysis of Floating Body Effects in Thin Film Conventional and Single Pocket SOI MOSFETs using the GIDL Current Technique
(IEEE, 2001-07) Rao, V. Ramgopal
In this paper, we present an analysis of floating body effects in lateral asymmetric channel (LAC) and conventional homogeneously doped channel (uniform) SOI MOSFETs using a novel gate-induced-drain-leakage (GIDL) current technique. The parasitic bipolar current gain /spl beta/ has been experimentally measured for LAC and uniform SOI MOSFETs using the GIDL current technique. The lower parasitic bipolar current gain observed in LAC SOI MOSFETs is explained with the help of 2D device simulations.
Analysis of floating body effects in thin film SOI MOSFETs using the GIDL current technique
(IEEE, 2001-07) Rao, V. Ramgopal
In this paper, we present an analysis of floating body effects in lateral asymmetric channel (LAC) and conventional homogeneously doped channel (uniform) SOI MOSFETs using a novel gate-induced-drain-leakage (GIDL) current technique. The parasitic bipolar current gain /spl beta/ has been experimentally measured for LAC and uniform SOI MOSFETs using the GIDL current technique. The lower parasitic bipolar current gain observed in LAC SOI MOSFETs is explained with the help of 2D device simulations.
Analysis of Threshold Voltage Variation in Fin Field Effect Transistors: Separation of Short Channel Effects
(IOP, 2020-04) Rao, V. Ramgopal
The variation in the threshold voltage caused by fluctuations in a device parameter is given by the product of a sensitivity coefficient and the fluctuation amount. In this paper, the sensitivity coefficient for each device parameter was separated into two factors: one due to an intrinsic mechanism [one-dimensional (1D) factor] and another due to short-channel effects [two-dimensional (2D) factor]. Using this concept, the variations in the threshold voltage and the sensitivity coefficients in doped fin field effect transistors (FinFETs), undoped FinFETs and planar metal–oxide–semiconductor FETs (MOSFETs), whose structures are based on the ITRS, were evaluated for the fluctuations in the principal device parameters. It was found that the 2D factor rather than the 1D factor dominated the sensitivity coefficients, although the degree of domination varies between the fluctuating parameters. The 1D and 2D factors were found to cancel each other out, thereby reducing the sensitivity coefficient. Based on these results, FinFETs with various structures were examined and controlling short-channel effects was demonstrated to be an effective way to reduce the variation in the threshold voltage.
Analysis of Threshold Voltage Variations of FinFETs Relating to Short Channel Effects
(IOP, 2009) Rao, V. Ramgopal
Clarification of robustness for threshold voltage (Δth) variation in FinFETs is very important. Vth variation (ΔVth) caused by fluctuations of some principal device parameters are evaluated, compared to the planar MOSFETs. However, the origin of ΔVth is complex in short channel devices due to contribution of short channel effects (SCEs). Therefore, the origin of ΔVth is separated into two factors, that is, intrinsic factor which can be determined by Poisson's equation along M-O-S stack, called the 1D factor, and factors caused by SCEs, called 2D factors. The ΔVth is dominated by both factors on the planar MOSFETs, while it is dominated by the 2D factor on the FinFETs because the amount of spacer charge in the channel is small. Additionally, the Vth is studied in two advanced FinFET structures which show reduced SCEs.
Anhydrous silanization and antibody immobilization on hotwire CVD deposited silicon oxynitride films
(IEEE, 2004-12) Rao, V. Ramgopal
Hotwire CVD (HWCVD) deposited silicon rich nitride films were treated with O/sub 2/ plasma using RF plasma setup. The thickness of this oxynitride film was measured using spectroscopic ellipsometry. The film was treated with [3-(2-aminoethyl) aminopropyl]-trimethoxysilane (AEAPS) followed by immobilization of human immunoglobulin (HIgG) on it. Surface morphology at various stages of experimentation was studied using AFM. Antibody immobilized surface is further investigated using fluorescence microscopy.
Anomalous diffusion mediated kinetic modelling of surface-stress sensors
(Elsevier, 2016-01) Rao, V. Ramgopal
Diffusion kinetics over fractal geometries are governed by anomalous subdiffusion processes for non-energetically driven adsorption/desorption of analyte over the sensor surface. This paper proposes a more accurate model to analytically interpret and predict the sensor kinetics in microscopic domain and uses Langmuir adsorption isotherm to model its response.
Anomalous Width Dependence of Gate Current in High- K Metal Gate nMOS Transistors
(IEEE, 2015-08) Rao, V. Ramgopal
This letter analyzes the width dependence of gate current observed in nMOS transistors fabricated using the 28-nm gate-first CMOS process. It is experimentally shown that the gate current density is ~10× lower for 80-nm wide high permittivity (K) dielectrics and metal gate nMOS transistors compared with 1-μm wider ones. The physical mechanism responsible for this anomalous width dependence is identified and attributed to the reduction in the average number of positively charged oxygen vacancies present in HfO 2 for narrow width transistors.
Application of charge pumping technique for sub-micron MOSFET characterization
(Elsevier, 1998-11) Rao, V. Ramgopal
In this paper, charge pumping technique for MOSFET interface characterization will be reviewed. The basic principles of charge pumping technique will be elaborated and its evolution as an excellent tool for a thorough characterization of MOSFET interface properties will be illustrated. Published results regarding the applicability of charge pumping technique for a study of sub-micron MOSFET interface and its degradation under various electrical stress conditions and radiation will be analyzed. The effect of geometric components on charge pumping current as well as the recent reports of single interface trap characterization in sub-micron MOSFETs will be described. The application of charge pumping technique at cryogenic temperatures and in other MOS based devices will also be included.
Application of look-up table approach to high-K gate dielectric MOS transistor circuits
(IEEE, 2003-01) Rao, V. Ramgopal
In this paper, we study the circuit performance issues of high-K gate dielectric MOSFETs using the Look-up Table (LUT) approach. The LUT approach is implemented in a public-domain circuit simulator SEQUEL. We observed an excellent match between LUT simulator and mixed mode simulations using MEDICI. This work clearly demonstrates the predictive power of the new simulator, as it enables evaluation of circuits directly from device simulation results without going through model parameter extraction.
Application of Mono Layered Graphene Field Effect Transistors for Gamma Radiation Detection
(IEEE, 2018-10) Rao, V. Ramgopal
In this work, we report the application of graphene field effect transistors (GFETs) as a gamma radiation sensor. The GFETs were irradiated at room temperature by 60 Co gamma radiation source for 10 kGy and 20 kGy gamma dose. The Electrical measurements and Raman spectroscopy showed that gamma radiation induced p-doping in graphene. Large positive shifts in Dirac point and significant degradation in electron mobility were observed post-gamma irradiation. Thus modulation in transport properties of GFETs was utilized here to measure the absorbed gamma radiations. We propose, a GFET based radiation detector with high sensitivity of + 113 V for 20 kGy gamma dose operating in ambient condition.