BITS Faculty Publications
Permanent URI for this communityhttp://localhost:4000/handle/123456789/1867
Browse
10 results
Search Results
Item Physica Scripta On-Current Modeling of Polycrystalline Silicon Thin-Film Transistors(IOP, 2005) Gupta, NavneetWe propose an on-current (above threshold voltage) model of polycrystalline silicon thin-film transistors (poly-Si TFTs). The model includes the study of the effect of trap state density, poly-Si inversion layer thickness and temperature on the TFT characteristics. Effective carrier mobility and I-V characteristics are described by considering the mechanism of capture and release of carriers at grain boundary trap states and the thermionic emission theory. It is found that at low as well as at high doping concentrations, the effective carrier mobility (µeff) increases with increasing temperature whereas a dip is observed at intermediate doping concentration. At very high and very low doping concentration the effect of temperature on the mobility is found to be almost negligible. Calculations reveal that effective carrier mobility and drain current increase as the gate bias increases and are larger for a lower trap state density. The calculated value of activation energy decreases as the gate bias increases and is larger for a larger poly-Si inversion layer thickness. A comparison between the present predictions and the experimental results shows reasonably good agreement.Item Effect of Inversion Layer Thickness on the Activation Energy and Turn-On Characteristics of Polysilicon Thin-Film Transistors(World Scientific, 2005) Gupta, NavneetThe influence of inversion layer thickness on the activation energy and turn-on characteristics of a polycrystalline silicon thin-film transistor (poly-Si TFT) have been investigated theoretically by developing an analytical model. It is observed that activation energy decreases as the gate bias increases and is larger for a larger poly-Si inversion layer thickness. It is also observed that effective carrier mobility and drain current increase rapidly with the increase in gate voltage for all values of inversion layer thickness and are larger for lower inversion layer thickness. The computed results are in reasonable agreement with the experimental observations.Item Physica Scripta An Analytical Model of the Influence of Grain Size on the Mobility and Transfer Characteristics of Polysilicon Thin-Film Transistors (TFTs)(IOP, 2005) Gupta, NavneetInfluence of the grain size on the effective carrier mobility (μeff) and transfer characteristics of a polycrystalline silicon thin-film transistor (poly-Si TFT) has been theoretically investigated by developing an analytical model. The dependence of μeff is studied as function of doping concentration and gate voltage for different values of grain size. It is observed that at low as well as at high doping concentrations, the effective carrier mobility (μeff) increases with increasing grain size, whereas the observed dip at the intermediate doping concentration is confirmed. The effect of the grain size on transfer characteristics of poly-Si TFT in its linear region is also presented. It is found that at low gate voltages, μeff and ID increase rapidly with the increase in VG for all grain sizes due to the grain boundary barrier lowering effect. At high gate voltage the grain boundary barrier lowering effect becomes insignificant and causes the saturation of μeff and ID. The model was found to account correctly for the experimentally observed mobility variation and yield a reasonably good agreement.Item Analytical modeling of carrier transport through transverse and longitudinal grain boundaries in polysilicon thin-film transistors(The National Institute of Science Communication, 2006) Gupta, NavneetCarrier transport through transverse and longitudinal grain boundaries (GBs) in polysilicon thin film transistors (poly-Si TFTs) has been studied. The model considers an array of square grains in the channel of poly-Si TFT in which current flows along the longitudinal GBs and through the grains and the transverse GBs. The variation of field-effect mobility (HFE) and drain current (ID) is computed for different values of grain size. This study reveals that at low gate voltage the longitudinal GBs are seen to influence the field-effect mobility and drain current. As gate voltage increases, the effect of transverse GBs is found to account for experimental results. This is attributed to the fact that at low gate voltage, the carriers moving through longitudinal GBs have more opportunities to be trapped at the trapping sites and as gate voltage increases the carriers have sufficient energy to bypass the longitudinal GBs and obstructed by transverse GBs alone. This may be the reason that the calculated effects of longitudinal GBs do not appear in the experimental results at high gate voltageItem On the mobility, turn-on characteristics and activation energy of polycrystalline silicon thin-film transistors(Elsevier, 2006-05) Gupta, NavneetIn the present paper we propose a turn-on current model of polycrystalline silicon thin-film transistors (poly-Si TFTs). It is found that at low as well as at high doping concentrations, effective carrier mobility (μeff) increases with increase in temperature whereas a dip is observed at intermediate doping concentration. At very high and very low doping concentration the effect of temperature on the mobility is found to be almost negligible. Calculations reveal that effective carrier mobility and drain current increases as the gate bias increases and are larger for a lower trap state density. The calculated value of activation energy decreases as the gate bias increases and is larger for a larger poly-Si inversion layer thickness. A fair agreement is observed between the present predictions and the experimental results.Item Threshold voltage modelling and gate oxide thickness effect on polycrystalline silicon thin-film transistors(IOP, 2007-10) Gupta, NavneetThis paper presents an analytical model for calculating the threshold voltage in polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with large grains. In the present study, it is assumed that the oxide-silicon interface traps are uniformly distributed and the channel of the device contains only a single grain boundary. Further, the effect of gate oxide thickness on threshold voltage and hence on transfer characteristics has also been incorporated in this paper. It is observed that scaling down of the oxide thickness is an efficient way to reduce the threshold voltage and hence to improve the poly-Si TFT characteristics at different temperatures and trap densities. The results so obtained are compared with the available experimental data which show a satisfactory match thus justifying the validity of the model.Item Selection of Gate Dielectrics for ZnO based Thin-Film Transistors(Lietuvos mokslų akademija, 2016) Gupta, NavneetThe bulk of semiconductor technology has been based on silicon till today. But silicon has its own limitations. It is not transparent to visible light and hence it cannot be used in certain applications. ZnO is a material which is transparent to visible light. In this paper, we compare the electrical performance of ZnO Thin film Transistors using different gate insulators. Certain performance indices and material indices were considered as the selection criteria for electrical performance. A methodology known as Ashby’s approach was adopted to find out the best gate insulators and based on this methodology various charts were plotted to compare different properties of competing materials. This work concludes that Y2O3 is the best insulator followed by ZrO2 and HfO2.Item Zinc oxide Thin-Film Transistors: Advances, Challenges and Future Trends(BEEI, 2016-06) Gupta, NavneetThis paper presents a review on recent developments and future trends in zinc oxide thin film transistors (ZnO TFTs) together with challenges involved in this technology. It highlights ZnO TFT as next generation choice over other available thin film transistor technology namely a – Si: H (amorphous hydrogenated silicon), poly-Si (polycrystalline silicon) and OTFT (organic thin film transistor). This paper also provides a comparative analysis of various TFTs on the basis of performance parameters. Effect of high –k dielectrics, grain boundaries, trap densities, and threshold voltage shift on the performance of ZnO TFT is also explained.Item Investigations on high-κ dielectrics for low threshold voltage and low leakage zinc oxide thin-film transistor, using material selection methodologies(Springer, 2016-02) Gupta, Navneet; Kandpal, KavindraThis paper presents the investigations on high-κ dielectrics for low operating voltage and low leakage zinc oxide thin film transistor (ZnO TFT) using three material selection methodologies namely Ashby, technique for order preference by similarity to ideal solution (TOPSIS) and VlseKriterijumska Optimizacija I Kompromisno Resenjein in Serbian (VIKOR). Various material properties such as dielectric constant, conduction band offset to ZnO, band-gap and temperature coefficient mismatch of high κ to ZnO are investigated to find out the most promising gate dielectric material. The analysis concludes that lanthanum oxide (La2O3) is the most promising gate dielectric material for ZnO TFT transistor. The result shows a good agreement between Ashby’s, TOPSIS and VIKOR approaches.Item Adaptation of a compact SPICE level 3 model for oxide thin-film transistors(Springer, 2019-05) Gupta, Navneet; Kandpal, KavindraOxide thin-film transistors (TFTs) and metal–oxide–semiconductor field-effect transistors (MOSFETs) operate via different conduction mechanisms but exhibit similar device characteristics. In this work, a SPICE level 3 model originally defined for MOSFETs is successfully adapted to provide a behavioral model for oxide TFTs. This adapted compact model is applicable to all kinds of oxide TFTs, irrespective of the channel and dielectric material used. To capture the TFT behavior efficiently, the experimental characteristic of an oxide TFT is used to set various SPICE level 3 parameters.