Department of Electrical and Electronics Engineering

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    Mitigating Pillar-to-Pillar Variability of Ground Select Transistor in 3-D NAND Flash Memory
    (IEEE, 2020-08) Bhatt, Upendra Mohan
    The threshold voltage variability of the select transistors is an important issue in the development of 3-D NAND flash memory. Particularly, pillar-to-pillar variations in threshold voltage (VT) of the ground select transistor (GST) are critical across the wafer. The VT variation is attributed to the nonuniformity in the plug height of the epitaxially grown silicon layers in different pillars. In this article, we propose different techniques to achieve performance uniformity in different strings across the wafer in terms of VT distribution of GST. We show that by optimizing the channel doping and gate metal work function (WF) of the GST, the NAND string VT nonuniformity can be eliminated. It is also shown that VT variability can be further minimized by optimizing GST gate length. Further, we present a two-MOSFET model for the pillar-to-pillar VT variation across the wafer. This study providesimportant results for designing 3-D NAND memories with higher performance uniformity for the pillar-to-pillar variations in strings across the wafer.
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    Performance Enhancement by Optimization of Poly Grain Size and Channel Thickness in a Vertical Channel 3-D NAND Flash Memory
    (IEEE, 2018) Bhatt, Upendra Mohan
    String read current (Iread) reduction with rising mold height and grain boundary traps is one of the major hurdle in the development of 3-D NAND flash memory. In this paper, we have investigated Iread with variation in polysilicon channel grain size (GS), grain boundary trap density, and channel thickness (TSi), using TCAD. We find that under a critical value of GS, Iread decreases with increase in TSi. This is attributed to the fact that with smaller GS, the total number of grain boundaries and associated traps are significantly higher. Moreover, there exists a typical value of GS for which Iread is independent of TSi, which is desirable to minimize the deviations in Iread arising from TSi variations. The resulting tradeoff in the design of more efficient 3-D NAND flash is demonstrated and discussed. Further, it is found that Iread increases significantly by limiting the polysilicon channel grain boundary trap concentration under 1012 cm-2. The results presented in this paper are crucial for optimizing Iread and program/erase threshold voltage(VT) window, and serve as key guidelines in the design of 3-D NAND flash memory with better performance.