Department of Electrical and Electronics Engineering

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Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology
(Springer, 2019-02) Vidhyadharan, Sanjay
This paper presents the circuit performance of an optimized TFET device whose performance is not only better than most of the TFET devices reported in current literature, but exceeds the performance of state-of-the-art industry-standard 45 nm CMOS technology. Novel TFET structures have been proposed whose ON current (Ion) matches with that of the MOSFETs, while maintaining the OFF current (Ioff) at least 3 orders of magnitude lower than the MOSFETs with the same width and at the same technology node. The key performance metrics of the optimised TFET-based circuits have been benchmarked with similar CMOS-based standard digital circuits like the simple inverter, 2 input NAND gate, 2 input NOR gate, 2 input XOR gate, 6 transistor SRAM and 3 stage inverter chain. The overall improvement in Power Delay Product (PDP) of the TFET-based circuits has been demonstrated to be more than 97% lesser than the corresponding CMOS circuits.
Fast and Low-Power CMOS and CNFET based Hysteresis Voltage Comparator
(Taylor & Francis, 2023-01) Vidhyadharan, Sanjay
This paper presents CMOS and CNFET based hysteresis voltage comparators for low-voltage applications. The proposed CMOS and CNFET hysteresis comparators require merely 1.6 and 0.26 µW of power, respectively, which is less than one tenth of the power dissipated by the other advanced hysteresis comparators designs available in literature. The propagation delay observed in the proposed CMOS and CNFET hysteresis comparators are 162 and 47 ps, respectively, which is almost half the delay exhibited by the other hysteresis comparators. Overall, a 93–99% reduction in Power Delay Product (PDP) can be achieved. Furthermore, the proposed design requires only nine transistors compared to the 11–17 transistor requirement in conventional hysteresis comparators, thus saving up to 47% of chip area.
Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node
(Springer, 2020-01) Vidhyadharan, Sanjay
In this paper, four different types of gate-overlap tunnel FET (GOTFET) devices are proposed for ultra-low power applications: (1) generic GOTFETs for digital logic, (2) low- and high-threshold (LVT and HVT) GOTFETs for ternary logic, (3) multi-threshold GOTFETs giving both LVT and HVT characteristics by simply altering their terminal connections and (4) line-tunneling-based GOTFETs for analog applications. The most interesting feature of the proposed GOTFET is that in the same device structure, just by changing the material and doping parameters of the device, we can get the optimal performance for different applications. Each of these GOTFET structures have been optimized such that their characteristics are superior than equally sized 45-nm MOSFETs. Device optimization has been carried out by studying the impact of changes in various device parameters on performance. GOTFET characteristics were simulated using industry-standard synopsys® TCAD tools, while the benchmarking with an equivalent CMOS technology was carried out using the standard 45-nm CMOS library in industry-standard cadence® EDA tool. Proposed GOTFETs have minimum on-state currents Ion at least twice (Ion,GOT≥2Ion,MOS), with maximum off-state currents Ioff remaining at least an order of magnitude lower (Ioff,GOT≤0.1Ioff,MOS), than the corresponding equally sized MOSFETs at the same 45-nm technology node. Circuit analysis and designs are beyond the scope of this paper; however, the innovative GOTFETs proposed in this paper will serve as the basic active devices in digital, ternary logic and analog applications yielding circuit performance far superior to the state-of-the-art designs at the same technology node, as indicated in our previous reports.
An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger
(Elsevier, 2020-10) Vidhyadharan, Sanjay
This paper introduces an innovative Gate-Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield around double the on current Ion, while the off current Ioff remains around an order lower, than that of an analogous equally-sized MOSFET at the same technology node. Higher Ion: Ioff ratio and steeper sub-threshold slope of the proposed GOTFETs make them ideal candidates for ultra-low voltage applications like Schmitt trigger circuits. Considering the superior performance of the proposed GOTFET devices, simply replacing the MOSFETs with the proposed GOTFETs in conventional Schmitt trigger circuit significantly reduces the delays and static power consumption of the circuit as expected. At 0.4 V power supply voltage, there is 91.7% improvement in Power Delay Product (PDP) for Complementary GOTFET (CGOT) based conventional Schmitt trigger as compared to CMOS conventional Schmitt trigger for the same hysteresis width of 120 mV. In order to further minimize the dynamic power, a novel CGOT regenerative-latch Schmitt trigger design has also been presented in this paper for the first time, which further reduces the total (static + dynamic) power consumption and delays of the conventional Schmitt trigger circuit. The overall PDP in the proposed CGOT regenerative-latch based Schmitt trigger has been demonstrated to be merely 1.9% of (98.1% lower than) the PDP in corresponding CMOS conventional design.
Mux Based Ultra-Low-Power Ternary Adders and Multiplier implemented with CNFET and 45 nm MOSFETs
(Taylor & Francis, 2021-04) Vidhyadharan, Sanjay
This paper presents improved multiplexer-based ultra-low-power ternary Half Adder (HA), ternary Full Adder (FA), and ternary 1-bit multiplier designs. The proposed circuits consume 61–91% lesser power and can be implemented with 10–40% lesser number of transistors, as compared to the other corresponding circuits available in the literature. The reduction in power and transistor count has been achieved through improved multiplexer designs and judicious use of pass transistor logic. CNFETs have low gate capacitance and hence are ideal devices for ultra-low-power VLSI applications; however, CMOS technology is presently the most preferred technology, because of the easy and low-cost fabrication option made available by the well-established CMOS fabrication labs. Keeping this in view, the proposed mux-based ternary half adder has been designed with both 45 nm MOSFETs and CNFETs. The performance of the proposed HA design has been benchmarked with other CNFET HA reported in the literature. The proposed mux-based CNFET ternary HA, FA and 1-bit multiplier have 10–30% lesser propagation delays than the other designs available in the literature. The reduction in the Power Delay Product (PDP) is 85–99% in the proposed mux-based CNFET ternary circuits as compared to the other benchmarked designs.
Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications
(IEEE, 2019) Vidhyadharan, Sanjay
For the first time, innovative low (LVT) and high (HVT) threshold tunnel FET devices have been reported for ternary logic applications. Based on an iterative algorithm, the DG TFET structures have been optimized such that the TFET characteristics are better than the MOSFETs having same width at the standard 45 nm technology node. These devices are designed in such a way that the low and high threshold voltages are VTL = VDD/3 and VTH = 2VDD/3 respectively, with the ranges {0 to VDD/3}, {VDD/3 to 2VDD/3} & {2VDD/3 to VDD} representing the 3 logic states 0, 1 & 2 respectively. Device optimization has been carried out by studying the impact of changes in various device parameters on performance. Optimized TFET devices have been benchmarked with standard CMOS for the same circuit designed using same technology. TFET device characteristics were simulated using Synopsys TCAD tools and circuit performance benchmarking was carried out with the standard 45 nm CMOS library using cadence EDA tool. Proposed LVT & HVT TFETs have ON currents (ION) roughly twice and OFF currents (IOFF) at least an order of magnitude lower than the corresponding MOSFETs. The performance of the optimized TFET based NTI & PTI ternary logic cells have been benchmarked with analogous CMOS circuits at same technology node. The overall Power Delay Products (PDP) of the TFET based logic cells have been demonstrated to be around 99.9% lower than the corresponding CMOS based logic cells. The proposed LVT & HVT TFET based NTI and PTI cells will serve as the starting point for any ternary logic applications.
A novel ultra-low-power CNTFET and 45 nm CMOS based ternary SRAM
(Elsevier, 2021-05) Vidhyadharan, Sanjay
This paper presents a CNTFET based ultra-low-power ternary SRAM design which consumes merely 66 nW of power, achieving 84–98% reduction in power consumption as compared to the other CNTFET ternary SRAM designs reported in the literature. The 6-Transistor (6T) Standard Ternary Inverter (STI) cell or the 3T-STI cell form the basic building block of the conventional SRAM cells. These conventional STI designs have an undesirable direct path between VDD and ground during certain ternary input signals, resulting in higher power consumption. In this paper, a highly power-efficient 4T-STI based Ternary SRAM design is presented, which prevents a direct path between the power supply VDD and ground in all the possible ternary logic states. While CNTFET is preferred by many researchers around the world for low-power VLSI applications, CMOS technology is still widely used in the industry because of the availability of advanced CMOS manufacturing units. Therefore, the proposed ultra-low-power ternary SRAM design has been implemented with both 32 nm CNTFET and 45 nm CMOS devices. The performance of both the CNTFET and CMOS based ultra-low-power ternary SRAM circuits have been benchmarked with corresponding conventional SRAM circuits. The overall decrease in Power Delay Product (PDP) is 86–97% in the proposed ultra-low-power ternary 32 nm CNTFET SRAM circuit and 87–99% in the proposed 45 nm CMOS SRAM with respect to corresponding conventional ternary SRAM circuits.
A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder
(Taylor & Francis, 2020-03) Vidhyadharan, Sanjay
Recent researches have indicated that the gate-overlap tunnel FETs (GOTFETs) exhibit double the on-currentsIon and one-tenth the off-currents Ioff than the equally sized MOSFETs at the same technology node, making them ideal candidates for ultra-low-power VLSI applications. This paper presents a complementary GOTFET (CGOT) based dynamic full adder (DFA), which consumes significantly lower power than conventional CMOS DFAs and operates at double the speed of CMOS DFAs. A conventional DFA designed using GOTFETs instead of MOSFETs exhibits 100 ps (40%) lower & 50 ps (30%) lower delays than CMOS DFA. Furthermore, the CGOT DFA consumes merely 2.6 pW of static power, which is 99% (2 orders) lower than the corresponding CMOS DFA ., Ion, . This paper proposes a novel improved DFA circuit design, which mitigates the dynamic power by eliminating redundant switching activity within the DFA circuit, . The proposed modified DFA topology reduces the total power consumption by 25% than the conventional DFA designs at 50% switching activity. The overall power delay product (PDP) reduces to merely 0.9% of the standard CMOS designs. The total power consumption reduces even further with decreasing switching activity, and the improved CGOT DFA consumes 31% lower total power (at 25% switching activity).
TiO2−x–TiO2 Memristor Applications for Programmable Analog VLSI Circuits at 45 nm CMOS Technology Node
(Springer, 2020-10) Vidhyadharan, Sanjay
Memristor-CMOS (MCM) technology combines CMOS processing with nano-scale memristors enabling a significant reduction in the silicon area as compared to CMOS-only counterparts. Moreover, the non-volatile memory characteristics of the memristor offers opportunity for new and innovative MCM hybrid VLSI circuits that can outperform conventional CMOS designs. MCM based hybrid, homogeneous re-configurable architectures have already gained immense popularity among digital VLSI designers. This paper explores application of TiO2−x–TiO2 charge trap memristor for programmable analog VLSI applications. The threshold adaptive memristor SPICE model has been used to evaluate the performance of the memristor in electronic design automation tool in conjunction with 45 nm CMOS devices. A digitally controlled MCM analog buffer, MCM binary phase shift keying modulator and a variable gain MCM differential amplifier has been presented in this paper. The MCM analog buffer has 81% greater gain-bandwidth product than the corresponding CMOS-only buffer and has an attenuation of −32 dB when the control signal is low. A MCM differential amplifier is proposed whose gain can be varied in both directions by shifting the operating point of the memristor through control signals, proving the advantages of using MCM technology for automatic gain control and other programmable analog VLSI applications. A MCM BPSK modulator circuit is also proposed which occupies 37.2% lesser silicon area than the conventional CMOS-only BPSK modulators, thus illustrating the utility of memristor in analog switching circuits.
An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder
(Elsevier, 2021-01) Vidhyadharan, Sanjay
This paper presents an ultra-low-power ternary dynamic Half Adder (HA) design which consumes merely 83 nW of power, achieving a 66–90% reduction in power consumption as compared to the other designs reported in the literature. Conventional ternary circuit designs use single VDD power supply, which is not a power-efficient technique. In these designs, the intermediate ternary logic state (VDD/2) is generated by allowing a steady-state current through two diode-connected transistors connected in series and the output is obtained from the junction of the two transistors. The proposed dual-VDD HA design utilizes both the available ternary power supply voltages (VDD & VDD/2) and prevents direct path between the power supplies and ground, in all the three possible ternary logic output states, resulting in a significant reduction in power consumption. While Carbon Nanotube FETs (CNFETs) is preferred by many researchers around the world for low-power VLSI applications, CMOS technology is still widely used in the industry because of the availability of advanced CMOS manufacturing units. Therefore, the proposed dual-VDD ternary dynamic HA design has been implemented with both CNFET and 45 nm CMOS devices. The proposed CNFET HA has an average delay of merely 8.4 ps, which is lower than the delays experienced in conventional designs (16.5–60.5 ps). The overall decrease in Power Delay Product (PDP) is 72–98% in the proposed CNFET HA, with respect to the other designs reported in the literature.
An ultra-low-power CNFET-based improved Schmitt triggerdesign for VLSI sensor applications
(Wiley, 2020-11) Vidhyadharan, Sanjay
To enable easy integration of Internet of Things (IoT) sensors with digital verylarge scale integrtaion (VLSI) circuits, the interface circuits need to operateefficiently even at low power supply voltages, consuming minimum powerfrom the limited onboard supply source. Schmitt triggers have higher noisemargins and lower delays as compared to conventional static CMOS logic cir-cuits, at low-voltage levels and hence are being widely used in VLSI sensorapplications. Carbon nanotube FETs (CNFETs) haveION:IOFFandION:CGGratios significantly greater than the corresponding CMOS devices, and hencethey have been acknowledged as viable candidates to replace CMOS devices inultra-low-power VLSI circuits. This article presents an ultra-low-powerCNFET-based Schmitt trigger design, which consumes significantly lowerpower than the conventional design. The cause of the higher power consump-tion in conventional CMOS-based Schmitt trigger is the availability of a directpath betweenVDDand ground for a longer time duration, during switching.The short-circuit path in the conventional CMOS Schmitt trigger circuit is theresult of the design methodology adopted to obtain hysteresis in VTC curve.The threshold voltage of the CNFET can be easily configured by an appropri-ate selection of its chiral vector. This property of the CNFET has been used inthe implementation of a new, simple but effective Schmitt trigger, which mini-mizes the short-circuit currents, while providing the same hysteresis as that ofconventional design. The proposed circuit operates at 0.4 VVDDto cater forlow-voltage levels of VLSI sensor applications. The proposed CNFET-basedSchmitt trigger consumes only 0.002 times the power of conventional CMOSSchmitt trigger and operates 56 times faster than the conventional CMOSdesign. The overall PDP in the proposed CNFET-based Schmitt trigger hasbeen demonstrated to be merely 0.0003% of the PDP in corresponding conven-tional designs