Department of Electrical and Electronics Engineering

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Now showing 1 - 6 of 6
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    Dedicated hardware architecture for localizing iris in VW images
    (Elsevier, 2022-07) Asati, Abhijit; Gupta, Anu
    This study presents dedicated hardware for iris localization that can be used as a coprocessor in the development of real-time and low-cost embedded iris biometric systems. Though the hardware architecture is described for iris localization in the visible wavelength (VW) images, the concept used can be applied to near infrared (NIR) images as well. In general, the architecture can be used for a class of iris localization algorithms based on the edge-map generation and circular Hough transform (CHT). The architecture presented here generates the edge-maps for limbic and pupil boundary detection using median filtering followed by Sobel edge detection; however, an additional reflection removal module is used for pupil boundary detection. Further, the CHT hardware module detects circle in each edge-map. The proposed architecture was implemented in programmable logic of the Zynq-7000 SoC device from Xilinx. This hardware implementation gives an iris localization accuracy of 98.43% and average processing time of 5.148 ms for UBIRIS.v1 VW database images (200 × 150 pixel). The algorithm used is suitable for less unconstrained and frontal-view iris images captured with subjects’ active participation; however, the images may contain non-ideal issues such as reflection and occlusion by eyelids and eyelashes.
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    Dedicated hardware architecture for localizing iris in VW images
    (Elsevier, 2022-07) Asati, Abhijit; Gupta, Anu
    This study presents dedicated hardware for iris localization that can be used as a coprocessor in the development of real-time and low-cost embedded iris biometric systems. Though the hardware architecture is described for iris localization in the visible wavelength (VW) images, the concept used can be applied to near infrared (NIR) images as well. In general, the architecture can be used for a class of iris localization algorithms based on the edge-map generation and circular Hough transform (CHT). The architecture presented here generates the edge-maps for limbic and pupil boundary detection using median filtering followed by Sobel edge detection; however, an additional reflection removal module is used for pupil boundary detection. Further, the CHT hardware module detects circle in each edge-map. The proposed architecture was implemented in programmable logic of the Zynq-7000 SoC device from Xilinx. This hardware implementation gives an iris localization accuracy of 98.43% and average processing time of 5.148 ms for UBIRIS.v1 VW database images (200 × 150 pixel). The algorithm used is suitable for less unconstrained and frontal-view iris images captured with subjects’ active participation; however, the images may contain non-ideal issues such as reflection and occlusion by eyelids and eyelashes.
  • Item
    Dedicated hardware architecture for localizing iris in VW images
    (Elsevier, 2022-07) Asati, Abhijit; Gupta, Anu
    This study presents dedicated hardware for iris localization that can be used as a coprocessor in the development of real-time and low-cost embedded iris biometric systems. Though the hardware architecture is described for iris localization in the visible wavelength (VW) images, the concept used can be applied to near infrared (NIR) images as well. In general, the architecture can be used for a class of iris localization algorithms based on the edge-map generation and circular Hough transform (CHT). The architecture presented here generates the edge-maps for limbic and pupil boundary detection using median filtering followed by Sobel edge detection; however, an additional reflection removal module is used for pupil boundary detection. Further, the CHT hardware module detects circle in each edge-map. The proposed architecture was implemented in programmable logic of the Zynq-7000 SoC device from Xilinx. This hardware implementation gives an iris localization accuracy of 98.43% and average processing time of 5.148 ms for UBIRIS.v1 VW database images (200 × 150 pixel). The algorithm used is suitable for less unconstrained and frontal-view iris images captured with subjects’ active participation; however, the images may contain non-ideal issues such as reflection and occlusion by eyelids and eyelashes.
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    Iris localization based on integro-differential operator for unconstrained infrared iris images
    (IEEE, 2015) Gupta, Anu; Asati, Abhijit
    Iris localization is an important step for high accuracy iris recognition systems and it becomes difficult for iris images captured in unconstrained environments. The proposed method localizes irises in unconstrained infrared iris images having non-ideal issues such as severe reflections, eyeglasses, low contrast, low illumination and occlusions by eyebrow hair, eyelids and eyelashes. In the proposed method, the iris image is first preprocessed using morphological operation to remove reflections and make it suitable for subsequent steps. The proposed method detects pupil using Daugman's integro-differential operator (IDO) and iris's outer boundary is detected using proposed modified Daugman's IDO. The proposed method proposes a technique based on thresholding and morphological operation to reduce the number of pixels on which the IDO is applied for detecting pupil which improves the time performance and accuracy as well. The method was tested with CASIA-Iris-Thousand, version 4.0 (CITHV4) iris database which contains challenging images having non-ideal issues as described before. The average accuracy of the proposed method is 99.3% and average time cost per image is 1.86 seconds for CITHV4. The proposed method shows improvement in both accuracy and time when compared with some published state-of-the-art iris localization methods in the literature.
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    An Iris localization method for noisy infrared iris images
    (IEEE, 2015) Gupta, Anu; Asati, Abhijit
    Iris segmentation is an important step in iris biometrics and becomes more challenging when iris images are noisy. Iris segmentation process localizes iris in the iris image and detects eyelids also. The proposed method localizes iris in noisy frontal view iris images captured under near infrared (NIR) illumination and having noise issues such as lighting and specular reflections, eyeglasses, low contrast, non-uniform illuminations and occlusions by heavy eyebrows, eyelids, eyelashes and hair. The proposed method is based on circular Hough transform (CHT) and an integro-differential operator (IDO) derived by taking motivation from Daugman's IDO. The pupil is localized using image binarization followed by CHT based algorithm and iris's outer boundary is detected by searching a limited image domain for maximum gray difference between iris and sclera using the proposed IDO. The method was tested on noisy images from two public NIR iris databases: MMU V2.0 and CASIA-Iris-Thousand V4.0. The average accuracy of the proposed method is 99.05 % and average time cost per image is 415 ms. Comparison of results of the proposed method with some published state-of-art iris localization methods proves its novelty.
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    Hardware implementation of a novel edge-map generation technique for pupil detection in NIR images
    (Elsevier, 2017-04) Gupta, Anu; Asati, Abhijit
    This paper proposes an edge-map generation technique for pupil detection in near infrared (NIR) images and its hardware implementation. The proposed edge-map generation technique is based on generating two different edge-maps of same eye image using Gaussian filtering, image binarization and Sobel edge detection operations and then combining them to a single edge-map using intersection operation on binary images. This technique reduces the false edges drastically in the edge-map of eye image, which is desirable for accurate and fast pupil detection. Field programmable logic array (FPGA) based hardware implementation of the proposed technique is presented, which can be used in iris localization system on FPGA based platforms for iris recognition application. The proposed edge-map generation hardware is a parallel-pipelined implementation.