Department of Electrical and Electronics Engineering
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Item Verification of Hardware Resource Utilization through High Level Synthesis for FPGA Implementation(IEEE, 2023) Asati, Abhijit; Shenoy, Meetha V.Recently, there has been a sharp rise in demand for hardware implementations because of the improved accuracy of Convolutional Neural Networks (CNN) on a wide range of classification and recognition applications. To achieve the needed performance, they include heavy processor operations and memory bandwidth. For optimized hardware deployment, which necessitates thorough optimization of system architectures and algorithms to get particularly efficient designs, a target system’s hardware resources and an estimation of its performance at a greater degree of abstraction are crucial. Since the programmable hardware fabric may be customized for each unique network, Field Programmable Gate Arrays (FPGA) can accomplish this efficiency in this situation. This paper shows the high-level synthesis (HLS) of each of the different layers of optimized CNN using the MATLAB HDL coder. Along with its HDL resource utilization report, we also investigated the computational processes and hardware resource estimation of the previously developed optimized CNN. The hardware resources required by all the convolutional and fully connected layers of the optimized CNN matches exactly will the previously calculated resources. So, the hardware resource utilization is verified through HLS. The architecture takes fixed-point math into account. All layers are synthesized in Vivado 2022.2 with the Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit as the target.Item High-Level synthesis assisted design and verification framework for automotive radar processors(Elsevier, 2020-10) Asati, Abhijit; Shekhar, ChandraIn radar-based advanced driver assistance systems, baseband processing is necessary to detect the speed, distance, and angle of elevation of the target (e.g., vehicle, pedestrian, traffic sign, etc.). The target and the source often move at high speeds; therefore, the computation rate must be sufficiently high to perform actions (e.g., braking) in real-time. Software-based implementations of such systems fall short of the required performance, which has led to an increase in the popularity of custom hardware implementations, e.g., on field-programmable gate arrays (FPGAs). FPGAs also serve as platforms to develop software concurrent with system-on-chip (SoC) development, thereby decreasing the time to market. High-level synthesis (HLS) tools are gaining considerable attention in the very-large-scale integration design community because of their flexibility. In this paper, we propose a novel design and verification framework for a RADAR processing SoC. The framework is assisted by an HLS-based design scheme for the processor and supports the application of a real-world stimulus to register transfer-level design implementation running on FPGAs. Customer use cases for the distance and velocity calculations are executed in a pre-silicon environment using range and Doppler processing on the Xilinx Kintex-7(XC 7K 480T) FPGA. Our findings show that the proposed framework, based on MATLAB HDL Coder and HDL Verifier, is superior to similar implementations from prior research in terms of speed and FPGA resources. This is owing to the usage of appropriate HLS directives and the usage of a novel design method based on application-specific bit width for intermediate data nodes.Item Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis(Springer, 2021-07) Asati, Abhijit; Shekhar, ChandraThis paper proposes an area, speed and power-optimized band-pass digital signal processing filter targeted for Kintex-7 Field Programmable Gate Array device. The filter was designed using MATLAB and Simulink and code generated using HDL Coder from MathWorks. The implementation was created using a novel high-level synthesis design method, which reduces pessimism associated with bit-width constraints in synthesis for inputs, outputs, and intermediate data nodes. MATLAB HDL coder generated Register Transfer Level (RTL) code was implemented on Xilinx Kintex 7 using Vivado software. The obtained results are superior to those of previous implementations for exact filter specifications. We also performed an RTL simulation for the filter and compared the functional verification results with a golden double-precision implementation in MATLAB. The results suggest that constraining the bit width and pessimism reduction has less than 1% impact on the filter accuracy within limits specified by architecture specifications.Item Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm(Elsevier, 2021-02) Asati, Abhijit; Shekhar, ChandraHarris corner detection is an algorithm frequently used in image processing and computer vision applications to detect corners in an input image. In most modern applications of image processing, there is a need for real time implementation of algorithms such as Harris corner detection in hardware systems such as field-programmable gate arrays (FPGAs). FPGAs allow faster algorithmic throughput, which is required to match real time speeds or cases where there is a requirement to process faster data rates. High level synthesis tools offer higher abstraction level to designers with continued verification during the design flow and hence are getting popular with the design community. This paper proposes a high speed and area optimized implementation of a Harris corner detection algorithm. The proposed implementation was actualized using a novel high-level synthesis (HLS) design method based on application-specific bit widths for intermediate data nodes. Register transfer level (RTL) code was generated using MATLAB HDL coder for HLS. The generated hardware description language (HDL) code was implemented on Xilinx ZedBoard using Vivado software and verified for functionality in real time with input video stream. The obtained results are superior to those of previous implementations in terms of area(smaller gate count on target FPGA) and speed for the same target board.