Department of Electrical and Electronics Engineering
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Item Estimation of Optimal Buffering parameters for dynamic traffic intensity and its Architectures(2005) Chaubey, V.K.In this paper, we have undertaken the mathematical formulation for determining the required buffering time based on the traffic intensity on an all-optical network. The effect of design parameters on optical network containing proper buffer and control circuitry has been evaluated. Some of the buffering architectures have been suggested to provide different buffering times as governed by the diurnal traffic requirementsItem A New XOR-Free Approach for Implementation of Convolutional Encoder(IEEE, 2016-03) Chaubey, V.K.This letter presents a new algorithm to construct an XOR-Free architecture of a power efficient Convolutional Encoder. Optimization of XOR operators is the main concern while implementing polynomials over GF(2), which consumes a significant amount of dynamic power. The proposed approach completely removes the XOR-processing operation of a chosen nonsystematic, feed-forward generator polynomial and reduces the logical operators, thereby the encoding cost. Hardware (HW) implementation of the proposed design uses Read-only memory (ROM) with a preprocessed addressing operations to reduce ROM size by nearly 50%. The results of the new architecture reduce the dynamic power up to 21.4% and HW cost up to 15% with lesser design complexity as compared to conventional method. The Hardware cosimulation of the architecture is first validated and then implemented with Xilinx Virtex-V FPGA.