Department of Electrical and Electronics Engineering
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Item Low Power Cascaded Three Stage Amplifier with Multipath Nested Miller Compensation(IEEE, 2010) Chaturvedi, Nitin; Gupta, AnuThis paper proposes a design for a low power cascaded three stage Operational Amplifier, with frequency compensation by Nested Miller Compensation which could be made to operate at low voltage supplies. The multipath technique is used to increase the bandwidth by converting the system into a two stage amplifier at high frequencies. The Op-Amp is designed in 180 nm technology and operates at a 3 V power supply with a gain of 115 dB, bandwidth of 103 Mhz, phase margin of 45 degrees and a settling time of 80-90 ns. Graph and simulation results are provided to verify the performance and to demonstrate the advantages of this three stage cascaded topology.Item Low-voltage, low-power SRAM circuits using subthreshold design technique(IET, 2019-09) Asati, Abhijit; Gupta, AnuThis chapter explores the design space of proposed M7T, MPT8T, M8T, M9T and MI-12T SRAM cells implemented at 45 nm technology node which are suitable for subthreshold operation. For quick comparison, Figure 3.45 shows the comparative design space exploration (DSE) chart of SRAM cells at 45 nm technology, respectively. The thorough analyses on the impacts of read stability, write ability, average write delay, average read delay and leakage power consumption in hold mode have been summarized in Table 3.14. The proposed memory cells exhibit improvement in performance over C6T.Item Leakage Immune 9T-SRAM Cell in Sub-threshold Region(IAES, 2016) Gupta, Anu; Asati, AbhijitThe paper presents a variability-aware modified 9T SRAM cell. In comparison to 6T SRAM cell the proposed cell achieves 1.3× higher read-SNM and 1.77× higher write-SNM with 79.6% SINM (static current noise margin) distribution at the expense of 14.7× lower WTI (write trip current) at 0.4 V power supply voltage, while maintaining similar stability in hold mode. Thus, comparative analysis exhibits that the proposed design has a significant improvement, thereby achieving high cell stability at 45nm technology.Item Power-aware Design of Logarithmic Prefix Adders in Sub-threshold Regime: A Comparative Analysis(Elsevier, 2015) Gupta, Anu; Asati, AbhijitThis paper involves the design and comparative analysis of Han-Carlson and Kogge-Stone adders in sub-threshold regime using three different hybrid logic families. The performance metrics considered for the analysis of the adders are: power, delay and PDP. Simulation studies are carried out for 8, 16, 32 and 64 bit input data width. The proposed circuits show an energy efficient agreement with Spectre simulations using BSIM3v3 and BSIM4 models for 90 nm CMOS technology at 0.4 V supply voltage. The adder implementation outperforms its counterparts exhibiting low power consumption and lesser propagation delay as compared to conventional adders operated in the sub-threshold regionItem Differential Power Analysis Immune Design of FinFET Based Novel Differential Logic Gate(IEEE, 2019) Gupta, AnuDifferential Power analysis (DPA) method is frequently used for non-invasive side-channel attack to hack into the system. This paper proposes a novel DPA attack immune design of FinFET based logic gates which show dense distribution of autocorrelation with salience strength of 38.11%. The proposed design has highly regular structure with exactly similar evaluation path for both differential outputs, AND-NAND, and OR-NOR which can be easily extended for n-bit inputs. The design effort is minimal as proposed structure is such that AND-NAND design can be used to obtain OR-NOR function by just changing the placement of inputs. These gates take 40 ps to evaluate the logic and consume 4.69 μ W/cycle. The designs are simulated using Symica Custom IC Design toolkit with ASAP7-7nm FinFET Low Threshold Voltage (LVT) technology with power supply of 700 mV.Item Power and Area Efficient Intelligent Hardware Design for Water Quality Applications(International Frequency Sensor Association, 2018-11) Gupta, Anu; Gupta, RajivThe paper presents a power efficient and computationally less intensive intelligent hardware using artificial neural network for water quality applications. A compact Hardware Neural Network algorithm has been developed that takes four water quality parameters as the input vector and perform classification of the parameters using a Multilayer Perceptron Network. The computational complexity in the implementation of logistic function has been reduced at a mathematical level by use of approximation methods such as Pad===?=== approximation for exponential function and non- linear approximation for sigmoid function. The network improves accuracy of the output by learning by back-propagation of the error. Results show that non-linear approximation method is 34.13 % power efficient and utilizes 15.53 % less number of hardware resources in comparison to Pad===?===. ASIC implementation is compact and has 99 % less power consumption as compared to FPGA implementation of the same algorithm.Item Current-Mode PMOS capacitance multiplier(IEEE, 2017) Gupta, AnuThis paper presents a novel technique to achieve an effective capacitance, multiples of up to 40 times that of a capacitor embedded in electronic circuits thus minimizing the area of silicon die. The technique employed for multiplication is PMOS transistor based low-voltage cascode current mirroring consuming low-power. The proposed design, capable of achieving high multiplication factors, is simulated in Cadence using 180nm technology library. An application of the capacitance multiplier shifting the dominant pole by 254kHz of a 19.7dB gain common source amplifier is also presented.Item Quad-NMOS cross-coupling for linearity enhancement in high frequency continuous-time OTA-C filters with IM3 below −70 dB(IEEE, 2017) Gupta, AnuThis paper presents a technique to cancel nonlinearity in operational trans-conductance amplifiers for continuous-time high frequency (OTA)-C filters. The OTA's trans-conductance can be tuned from 40 to 177 μA/V, consuming 8.09 mW power at 40 μA/V with -77 dB IM3 at 25 MHz. Third-order inter-modulation components remain below -70dB up to 50 MHz trading-off with power consumption. The IM3 for a 8.445 MHz low-pass second-order filter implementation is -76.2 dB. The design works at the supply voltage of 3.3 V. The results presented here correspond to the designs simulated in Cadence using PDK 90nm technology library.Item A hardware optimized low power RNM compensated three stage operational amplifier with embedded capacitance multiplier compensation(IEEE, 2016) Gupta, AnuThis paper proposes a hardware optimized low power three stage compensated operational amplifier with a capability of driving a wide range of capacitive loads ranging from 200pF to 5nF. The amplifier is compensated by implementing Embedded Capacitance Multiplier (CM) Compensation on the outer Miller capacitor of traditional Reverse Nested Miller Compensation (RNMC) with a feed forward stage. This provides a unity gain bandwidth (UGB) greater than 1MHz and phase margin greater than 60° for the range of loads mentioned above. The circuit has a 100uW of DC power dissipation for a 2V supply. The proposed technique uses two compensation capacitances of 1pf and 500fF only. The design achieves a unity gain bandwidth of 9.227MHz at 500pF capacitive load. The simulation is carried for 180nm CMOS technology in Cadence Virtuoso environment.Item To predict the impact of passive architecture on the temperature conditions inside a building using ANN(IEEE, 2016) Gupta, Anu; Gupta, RajivThe environmental impact of the building industry is significant. The construction industry constitutes a major part of the world's total energy consumption. As a result, building designers have constantly been urged to pay attention to the energy economics of buildings. Green building practices like passive solar building design, advanced construction, and building operation practices have been evolved over the years. Passive solar architecture basically refers the usage of structural and non-structural elements of the building for the comfort conditions with no additional operational costs. It makes the best possible use of the local geographic and climatic conditions. Such measures help in decreasing the operational costs of a building and increasing the thermal comfort of its occupants often leading to enhanced productivity. These energy efficiency measures also improve building marketability as the cost of operation is reduced. The temperature inside a building is one of the factors to identify the comfort level up to a great extent. Hence, it necessary to predict the internal air temperatures of any building. With this study, an attempt has been made at developing mathematical models that could predict the air temperature inside any building. The works attempts the development of a neural network regression tool which can predict the temperature inside a simple construction when fed with various building specifications as input. The results of this Artificial Neural Network were found to be in close agreement with the actual on-site recorded data. This is the first time that ANN is being used for such application. For the purpose of validation and testing, the data recorded for four rooms varying in architectural aspects over the past year have been taken. These recordings were taken on an hourly basis.