Department of Electrical and Electronics Engineering
Permanent URI for this collectionhttp://localhost:4000/handle/123456789/1925
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Item Performance exploration of adder architectures for small to moderate‐sized low‐power, high‐performance adders(Emerald, 2005-12) Gupta, Anu; Shekhar, ChandraThe objective is to explore various adder architectures using different logic‐design styles and transistor‐sizes for different operand sizes. The scope of this work is the development of tools, which can be used to predict an optimum adder design for a given application based on the speed and energy‐consumption constraintsItem Dual channel addition based FFT processor architecture for signal and image processing(ACM Digital Library, 2009-12) Gupta, Anu; Shekhar, Chandra; Asati, AbhijitThis paper presents a novel fixed-point 16-bit word-width 16-point FFT/IFFT processor architecture designed primarily for the signal and image processing application. The 16-point FFT is realised by using Cooley-Tukey decimation in time algorithm. This approach reduces the number of required complex multiplications compared to a normal discrete Fourier transform. Since multipliers are very power hungry elements in VLSI designs, they result in significant power consumption. So, the complex multiplication operations are realised using shift-and-add operations. The proposed algorithm performs all intermediate addition operation using a novel dual channel addition technique, which avoids carry propagation delay. Only in the last stage, carry look ahead adders are used to give final result. This dual channel addition algorithm reduces the critical delay path by 42% and 38.29% as compared to traditional and Maharatna approach respectively.Item Memory-efficient architecture of circle Hough transform and its FPGA implementation for iris localisation(IET, 2018-10) Gupta, Anu; Asati, AbhijitThis study presents a circle Hough transform (CHT) architecture that provides memory reduction between 74 and 93% without and with little degradation in the accuracy, respectively. For an image of P × Q pixels, the standard (direct) CHT requires a two-dimensional (2D) accumulator array of P × Q cells, but the proposed CHT uses a 2D accumulator array of (P/m) × (Q/n) cells for coarse circle detection and two 1D accumulator arrays of P × 1 and Q × 1 cells for fine detection, therein reducing the memory by a factor of m × n (approximately). The proposed CHT architecture was applied to iris localisation application and carried out its comprehensive evaluation. The average accuracy of the proposed CHT for iris localisation (inner plus outer iris-circle detection) is 98% with memory reduction of 87% compared with the direct CHT. The proposed CHT architecture was implemented on field programmable logic array targeting Xilinx Zynq device. The proposed CHT hardware takes processing time of 6.25 ms (average) for iris localisation in an image of 320 × 240 px2. The proposed work is compared with the previous work, which shows improved results. Finally, the effect of additive Gaussian noise on the CHT performance is investigated.