Department of Electrical and Electronics Engineering
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Item Design and Analysis of Modified Strong Arm Latch Comparator with Reduced Kickback Noise(Springer, 2024-10) Gupta, Anu; Shekhar, Chandra; Chaturvedi, NitinThis research paper introduces three techniques to reduce kickback noise in the Strong Arm Latch Comparator (SAL). The first technique focuses on utilizing high clock power and generating two clocks with different duty cycles. While initially addressing the issue by applying a single clock to the kickback-reducing circuit, the reduction of kickback noise did not meet the desired level. To overcome this limitation, a new design is proposed, incorporating a delay in the programmability of the kickback-reducing circuit, which effectively eliminates the need for kickback and clock requirements. A comparative study is conducted, evaluating all the designs, including the proposed design, based on power, delay, and analysis of various types of noise. Results show that the proposed technique outperforms other kickback-reducing designs in terms of propagation latency, power consumption, and kickback currents. Additionally, the impact of a comparator’s common-mode voltage (Vcm) on its performance in TSMC 180 nm CMOS technology is demonstrated using the Cadence Schematic Editor tool.Item Effectiveness of body bias & hybrid logic: An energy efficient approach to design adders in sub-threshold regime(Inder Science, 2016) Gupta, Anu; Asati, AbhijitRapid increases in chip complexity, increasingly faster clocks and proliferation of portable devices have combined to make power dissipation an important design parameter. In battery operated digital devices the demand of low power consumption and low energy dissipation in order to maximise battery life are the matter-of-course. Typical energy optimisation measures include voltage scaling and operating at the slowest possible speed. In this paper, to satisfy the low power requirement, sub-threshold logic that involves scaling voltage below the device threshold is being used. The proposed implementation lays emphasis on the usage of hybrid logic with reverse body biasing schemes which reduces high power consumption while giving lesser propagation delay and lesser area in sub-threshold regime. This scheme has been demonstrated on 4-bit, 16-bit and 64-bit carry look-ahead adders and simulated using TSMC 180 nm CMOS technology at 0.4 V supply voltage. Post-layout simulations show significant improvement, exhibiting low power consumption and lesser propagation delay as compared to conventional carry look-ahead adderItem Characterization of Logical Effort for Improved Delay(Springer, 2013) Gupta, AnuIn this paper, an effort has been made to improve the delay of a gate by skewing the gates by choosing proper sizing. The expression for skewed logical effort has been derived for universal logic gates namely NOT, NAND and NOR for minimizing the delay. The validations for minimum delay through simulation was done on a chain of inverters. The improved skewed gates showed 10% - 20% delay reduction on a chain of inverters as compared with normal skewed gate, high and low skewed gates, whereas, an improvement of 20% - 25% when compared to skewed gates favoring a particular transition. All simulations are done using Spectre in Cadence environment in UMC90nm CMOS technology at 1V power supply.Item A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers(IEEE, 2009) Gupta, AnuA very simple technique to achieve low settling time is presented. It is based on the combination of class AB differential input stages, local common-mode feedback (LCMFB), and clamping circuit which provides additional current boosting, keeping the gain-bandwidth product (GBW) nearly constant. The slew enhancement is provided by an auxiliary circuit which is activated only during transients. The design is based on the ldquoTSMC 180 nm CMOS technologyrdquo