Department of Electrical and Electronics Engineering
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Item VLSI for embedded intelligence:(Springer, 2025) Gupta, Anu; Chaturvedi, NitinThis book constitutes the proceedings of the 27th International Symposium on VLSI Design and Test, VDAT 2023. The 32 regular papers and 16 short papers presented in this book are carefully reviewed and selected from 220 submissions. They are organized in topical sections as follows: Low-Power Integrated Circuits and Devices; FPGA-Based Design and Embedded Systems; Memory, Computing, and Processor Design; CAD for VLSI; Emerging Integrated Circuits and Systems; VLSI Testing and Security; and System-Level Design.Item A comprehensive survey on data converters for IOT applications: scope, issues, and future directions(IEEE, 2025-03) Gupta, Anu; Shekhar, Chandra; Chamola, VinayData converters significantly contribute to efficient and accurate data processing in Internet of Things (IoT) systems. As IoT expands into agriculture, industrial automation, and healthcare (AIH), precise and low-power data conversion has become crucial to support longer battery life and reliable performance in IoT devices. Efficient data converters are key to reducing energy use, especially in components like comparator circuits, which consume significant energy in successive approximation register analog-to-digital converters (SAR ADCs). This survey provides an in-depth review of recent developments in low-power data converter design, examining techniques that help reduce power consumption at various stages. It emphasizes advancements, such as energy scaling, dynamic voltage references, and architectural optimizations that enhance efficiency without compromising performance. A specific analysis of emerging technology trends, such as the application of machine learning in data converter design, is explored to stimulate further innovation. Machine learning (ML)-based optimization, including adaptive calibration, noise reduction, and real-time performance optimization, presents new opportunities for enhancing efficiency and accuracy while addressing critical design constraints in IoT applications. While quantum encryption offers promising advancements in securing IoT data transmission, a broader security perspective beyond encryption is necessary, including concerns, such as attack detection and data integrity, ensuring the robustness of IoT systems. This review also examines latency, signal integrity, and accuracy issues, offering a roadmap for next-generation converter designs and reducing power consumption in data converters, which are fundamental to enhancing the performance and lifespan of IoT devices.Item A 12.11 mW, 99 pJ/Conv.-Step SAR ADC with Optimal Power Efficiency for IoT(IEEE, 2024-12) Gupta, Anu; Shekhar, ChandraThis brief presents a capacitive charge scaling DAC architecture with a two-phase non-overlapping clocking scheme to make an energy-efficient Successive Approximation Register (SAR) data converter for Internet-of-Things (IoT) applications. The proposed architecture comprises a Track & Hold (T/H), a Modified Strong Arm Latch comparator (MSAL), a SAR Control logic, and a digital-to-analog (D/A) converter. The proposed work is simulated using Cadence Virtuoso in TSMC 180 nm and achieves a minimum sampling rate of 1 MS/s and power consumption of 12.11 mW. To address the effects of process variations and mismatches on ADC performance, this paper conducts a thorough 500-point Monte Carlo (MC) simulation of the proposed SAR ADC circuit. The measured results show a Signal-to-Noise Ratio (SNR) of 47.81 dB, a Spurious-Free Dynamic Range (SFDR) of 54.32 dB, and ENOB of 7.65 Bits.Item Design & Analysis of Performance-efficient Comparator for IoT Application(IEEE, 2022) Shekhar, Chandra; Gupta, AnuThe regenerative latch comparator prototype for high-speed up to 1 Giga Hertz analog-to-digital conversion is shown in this article. Cascading structure of different modules makes the proposed comparator a suitable choice for various converters like SAR, Pipelined, Flash, etc. The proposed comparator achieves efficiency in terms of propagation latency, power consumption, and area as compared to the present state of the art mentioned in this work. Additionally, it uses the cadence schematic editor tool to illustrate how the performance of a comparator changes depending on its common-mode voltage (Vcm) and input (Vid) on TSMC 180 nm CMOS technology.Item Energy Efficient Hardware Implementation of 2-D Convolution for Convolutional Neural Network(IEEE, 2022) Gupta, AnuOver the last year, Deep neural networks (DNN) have been significantly accepted for computer vision applications because of high classification accuracy and versatility. Convolutional Neural Network (CNN) is one of the most popular architectures of DNN which is widely adopted for image, speech and video recognition. Extensive computation and large memory requirement of CNN s poses the bottleneck on its application. Field Programmable Gate Arrays (FPGAs) are considered to be suitable hardware platforms for deployment of CNNs with low power requirements. This paper focus on the design and implementation of hardware accelerator to perform the convolution product (matrix-matrix multiplication. We have used two optimization techniques to achieve energy efficiency. First, dataflow of the convolution phase is rescheduled to reduce the undesired on-chip memory accesses. Further, efficiency is enhanced by reducing the internal parallelism of structure as much as possible. Our architecture is implemented on the Xilinx ZCU104 evaluation board. The implemented design attains 98.1 GOPS/Joule and 32.77 GOPS/Joule for 8-bit and 16-bit data width respectively.Item Dedicated hardware architecture for localizing iris in VW images(Elsevier, 2022-07) Asati, Abhijit; Gupta, AnuThis study presents dedicated hardware for iris localization that can be used as a coprocessor in the development of real-time and low-cost embedded iris biometric systems. Though the hardware architecture is described for iris localization in the visible wavelength (VW) images, the concept used can be applied to near infrared (NIR) images as well. In general, the architecture can be used for a class of iris localization algorithms based on the edge-map generation and circular Hough transform (CHT). The architecture presented here generates the edge-maps for limbic and pupil boundary detection using median filtering followed by Sobel edge detection; however, an additional reflection removal module is used for pupil boundary detection. Further, the CHT hardware module detects circle in each edge-map. The proposed architecture was implemented in programmable logic of the Zynq-7000 SoC device from Xilinx. This hardware implementation gives an iris localization accuracy of 98.43% and average processing time of 5.148 ms for UBIRIS.v1 VW database images (200 × 150 pixel). The algorithm used is suitable for less unconstrained and frontal-view iris images captured with subjects’ active participation; however, the images may contain non-ideal issues such as reflection and occlusion by eyelids and eyelashes.Item Dedicated hardware architecture for localizing iris in VW images(Elsevier, 2022-07) Asati, Abhijit; Gupta, AnuThis study presents dedicated hardware for iris localization that can be used as a coprocessor in the development of real-time and low-cost embedded iris biometric systems. Though the hardware architecture is described for iris localization in the visible wavelength (VW) images, the concept used can be applied to near infrared (NIR) images as well. In general, the architecture can be used for a class of iris localization algorithms based on the edge-map generation and circular Hough transform (CHT). The architecture presented here generates the edge-maps for limbic and pupil boundary detection using median filtering followed by Sobel edge detection; however, an additional reflection removal module is used for pupil boundary detection. Further, the CHT hardware module detects circle in each edge-map. The proposed architecture was implemented in programmable logic of the Zynq-7000 SoC device from Xilinx. This hardware implementation gives an iris localization accuracy of 98.43% and average processing time of 5.148 ms for UBIRIS.v1 VW database images (200 × 150 pixel). The algorithm used is suitable for less unconstrained and frontal-view iris images captured with subjects’ active participation; however, the images may contain non-ideal issues such as reflection and occlusion by eyelids and eyelashes.Item Comparative Analysis of Phase/Frequency Detector in a Complete PLL System(IEEE, 2023) Gupta, Anu; Shekhar, ChandraIn many integrated radio frequency (RF) transceivers, the phase-locked loop (PLL) serves as a frequency synthesizer. This work goes to test various different phase/frequency detector blocks with a standard charge pump and Voltage controlled oscillator design. These include the comparison of different phase-frequency detectors (PFD) based upon D-flipflops, latches (Latch PFD) & pass transistors (PTPFD) to the more complex Pre-charged PFD. The best results of the PFDs in the PLL system in order are Pre-charge PFD, PT-PFD, Latch PFD and D-flipflop PFD. A charge pump PLL (CPLL) with a frequency range of [80 MHz -800 MHz] is simulated using Cadence Virtuoso (Spectre) at 180nm technology (scl\_pdk) with 1.8 V supply voltage. The phase noise of the VCO is less than -50dBc/Hz at 10MHz and is closer to 110dBc/Hz at 1GHz.Item Efficient ASIC Implementation of Artificial Neural Network with Posit Representation of Floating-Point Numbers(Springer, 2023-07) Gupta, Anu; Gupta, RajivThis paper presents a low-power ASIC architecture of a feedforward Artificial Neural Network using Posit representation. The ASIC Posit shows 50% improvement over ASIC using IEEE 754 format in terms of Power and Silicon Area and is also 13% faster while achieving the same accuracy. The same design using the FPGA platform consumes more power than the ASIC design. The designs are done using Cadence RTL Encounter with TSMC 180 nm technology node.Item Comparative Analysis of D/A Converter Architectures for SAR ADC(IEEE, 2024-02) Gupta, Anu; Shekhar, ChandraThis study gives an in-depth analysis of the architectures utilized in the analog-to-digital conversion process. The paper encompasses the design, performance, and suitability of the binary-weighted (charge distribution), R-2R ladder, and C-2C Digital-to-Analog (D/A) Converter architectures. This paper's discussed D/A converter architectures are simulated through the cadence tool using 180 nm CMOS technology. Based on comparative performance analysis, the C-2C D/A converter gives optimum results in terms of power, speed, DNL, INL, and settling time while maintaining its resolution. C-2C D/A converter reported a 63.15% improvement in power consumption compared to R-2R DAC, DNL, and INL errors below 0.01 LSB.