Department of Electrical and Electronics Engineering
Permanent URI for this collectionhttp://localhost:4000/handle/123456789/1925
Browse
3 results
Search Results
Item Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort(IEEE, 2022-12) Mishra, NeerajA static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging-aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage (Vth) of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time ( t ). A device-level approach for Vth degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of t . A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre- and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with t to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre- and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in the Eldo SPICE environment with the 65-nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.Item Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure(IEEE, 2023-07) Mishra, NeerajThis article proposes a method for performing device-level variability-aware static timing analysis (STA) on digital circuits using a tool flow methodology based on Python and Bash scripting. The method involves creating an effective current source model (ECSM) .libs file with a custom tool flow, which incorporates variation-aware timing models of standard cells to minimize recharacterization efforts. The resulting file is integrated into an industry-standard STA tool environment to assess the impact of device and layout level variability on digital timing closure. The simulation work is carried out using Mentor Graphics ELDO SPICE, Synopsys DC Compiler, and PrimeTime STA environment in STMicroelectronics (STM) 65 nm CMOS process. This tool flow reduces recharacterization efforts by 98.13% compared to conventional SPICE simulation by incorporating the impact of device-level variability on the conventional STA flow.Item Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis(IEEE, 2024-05) Mishra, NeerajWe propose switching activity factor-based effective current source model (SAFE) for aging-aware static timing analysis (STA), a new technique for estimating the timing performance of digital circuits. SAFE is based on the development of device-level variation-aware analytical timing models of stacked and multistage logic cells (commonly employed transistor topologies in a synthesized netlist of a random logic path), which drastically reduces the recharacterization efforts of the standard cells. The models developed are derived as a function of input transition time (TR) and load capacitance (CL) . The timing performance of a standard cell degrades with threshold voltage (Vth) degradation in a MOS device due to various aging mechanisms. SAFE, makes the entire STA process aging aware by updating its model coefficients with Vth degradation caused by aging. It is achieved by proposing a method for estimating Vth degradation under various stress conditions, including static, dynamic, and asymmetric, that applies to any process design kit (PDK). To consider asymmetric aging, we have developed a method to find effective switching activity factor (αeff) for N-stage stacked and N-stage parallel logic which is used to find the value of switching activity factor (α) at intermediate nodes in pipelined logic circuits. Our simulations are performed in Mentor Graphics Eldo SPICE environment using STMicroelectronics 28 and 65-nm CMOS process. The proposed technique provides a high-simulation accuracy (2.5% average error) when compared with SPICE simulations. Finally, we achieved a ~98.14% reduction in the required number of simulations using SAFE when compared with a completely SPICE/Aging simulation-based approach.