Department of Electrical and Electronics Engineering

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Author: search.filters.author.Rao, V. RamgopalSubject: search.filters.subject.Hysteresis

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    Hysteresis behavior in 85-nm channel length vertical n-MOSFETs grown by MBE
    (IEEE, 1996-06) Rao, V. Ramgopal
    Vertical n-MOSFETs with channel lengths of 85 nm have been grown by MBE. For drain-to-source voltages V/sub DS/>3.3 V, these transistors exhibit hysteresis behavior similar to the reported behavior of fully depleted SOI-MOSFETs. Our results also show a gate voltage controlled turn-off of the drain current when the transistor is operating in the hysteresis mode. We have analyzed this behavior in vertical n-MOSFETs using 2-D device simulation and our results show a threshold value for the hole concentration across the source-channel junction which is required for the forward biasing of this junction. For a transistor operating in the hysteresis mode, we show that the potential barrier height for electron injection across the source-channel junction increases for increasing negative gate voltages during retrace. This results in a gate controlled turn-off of the drain current for SOI and vertical n-MOSFETs operating in the regenerative mode.
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    Border-Trap Characterization in High-κ Strained-Si MOSFETs
    (IEEE, 2007-08) Rao, V. Ramgopal
    In this letter, we focus on the border-trap characterization of TaN/HfO 2 /Si and TaN/HfO 2 /strained-Si/Si 0.8 Ge 0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-kappa films on strained- Si/Si 0.8 Ge 0.2 .These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-kappa films on strained-Si are also proposed.
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    Electret mechanism, hysteresis, and ambient performance of sol-gel silica gate dielectrics in pentacene field-effect transistors
    (IEEE, 2007-12) Rao, V. Ramgopal
    The electret induced hysteresis was studied in sol-gel silica films that result in higher drain currents and improved device performance in pentacene field-effect transistors. Vacuum and ambient condition studies of the hysteresis behavior and capacitance-voltage characteristics on single layer and varying thicknesses of bilayer dielectrics confirmed that blocking layers of thermal oxide could effectively eliminate the electret induced hysteresis, and that thin (25nm) sol-gel silica dielectrics enabled elimination of nanopores thus realizing stable device characteristics under ambient conditions.
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    Sub-50-mV Nanoelectromechanical Switch Without Body Bias
    (IEEE, 2020-09) Rao, V. Ramgopal
    This brief presents a fabricated and characterized 3-terminal (3T) nanoelectromechanical switch (NEMS) featuring for the first time a sub-50-mV pull-in voltage operation without body biasing. The proposed NEMS demonstrates a low hysteresis (<; 20 mV), low turn-on delay (15 ns), and record low subthreshold slope of 2 mV/decade due to the small air gap of only 100 nm between the gate and the source beam realized using a simple and low-cost fabrication process. NEMS is a propitious candidate toward ideal switch exhibiting a zero leakage with ON-state conductance of 0.1 A.V/μm and a sub-50-mV swing providing an ultralow active power consumption.