Department of Electrical and Electronics Engineering
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Item Performance optimization of 60 nm channel length vertical MOSFETs using channel engineering(IEEE, 2001) Rao, V. RamgopalA comprehensive study has been performed to optimize the electrical characteristics of delta doped channel MOSFETs (D2FETs) having channel length of 60 nm. Extensive 2D device simulations have been employed to show that D2FETs exhibit higher drain current drive and reduced short channel and hot carrier effects compared to MOSFETs having uniform channel doping. The improvement has been found significant when the delta peak is shifted near the source end of the channel. Device simulations show acceptable short channel effects for 60 nm D/sup 2/FETs when the gate oxide thickness is reduced to the 2.5-3 nm regime.Item Device-circuit co-design for high performance level shifter by limiting quasi-saturation effects in advanced DeMOS transistors(IEEE, 2016) Rao, V. RamgopalThis paper presents a device-circuit co-design methodology for a DeMOS 5V GHz-speed high voltage level shifter. The limiting quasi-saturation effect is addressed by a codesign methodology. The co-design methodology is applied to the STI-DeMOS in a calibrated setup using experimental data. As a result, a 15% improvement in the speed is achieved for a high-performance level shifter circuit.