Department of Electrical and Electronics Engineering
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Item Performance exploration of adder architectures for small to moderate‐sized low‐power, high‐performance adders(Emerald, 2005-12) Gupta, Anu; Shekhar, ChandraThe objective is to explore various adder architectures using different logic‐design styles and transistor‐sizes for different operand sizes. The scope of this work is the development of tools, which can be used to predict an optimum adder design for a given application based on the speed and energy‐consumption constraintsItem Dual channel addition based FFT processor architecture for signal and image processing(ACM Digital Library, 2009-12) Gupta, Anu; Shekhar, Chandra; Asati, AbhijitThis paper presents a novel fixed-point 16-bit word-width 16-point FFT/IFFT processor architecture designed primarily for the signal and image processing application. The 16-point FFT is realised by using Cooley-Tukey decimation in time algorithm. This approach reduces the number of required complex multiplications compared to a normal discrete Fourier transform. Since multipliers are very power hungry elements in VLSI designs, they result in significant power consumption. So, the complex multiplication operations are realised using shift-and-add operations. The proposed algorithm performs all intermediate addition operation using a novel dual channel addition technique, which avoids carry propagation delay. Only in the last stage, carry look ahead adders are used to give final result. This dual channel addition algorithm reduces the critical delay path by 42% and 38.29% as compared to traditional and Maharatna approach respectively.