Department of Electrical and Electronics Engineering

Permanent URI for this collectionhttp://localhost:4000/handle/123456789/1925

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Author: search.filters.author.Shenoy, Meetha V.

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    HAFedL: a hessian-aware adaptive privacy preserving horizontal federated learning scheme for IOT applications
    (IEEE, 2024-09) Shenoy, Meetha V.
    Federated Learning (FL) is a paradigm in distributed machine learning, which has gained significant attention in the recent years especially in the domain of Internet of Things. Federated Learning saves communication bandwidth when compared to centralized machine learning process and is also considered to be privacy preserving as the raw data at the clients need not be transmitted to the server for the FL learning. Recent studies on FL have exposed privacy vulnerabilities particularly in the form of Gradient Leakage Attacks (GLA) in which the adversaries can generate training data of the client from shared gradients or model updates from clients. The available solutions in the literature for GLA based on perturbing the gradients from clients leads to a drop in the performance of the FL system while attempting to preserve privacy. We propose HAFedL, an improved novel hessian aware adaptive privacy preserving FL scheme in which the performance of the model is not significantly affected due to the aspects introduced in the FL architecture to improve the privacy of the model against the GLA. The HAFedL is also robust to the data heterogeneity and device heterogeneity (particularly straggler effect) which may be present in the clients participating in the FL. The performance of HAFedL is tested for two applications- IoT device identification and digit classification. The proposed HAFedL scheme can be utilized in privacy sensitive domains such as smart city applications, Industrial Internet of Things, Internet of Robotic Things, Internet of Medical Things, etc.
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    Efficient edge AI implementation for IoT device identification for hierarchical federated learning
    (Inder Science, 2025-03) Shenoy, Meetha V.
    As IoT devices proliferate, efficient IoT device identification is crucial for resource management, planning, and detecting anomalous traffic. Traditional ML-based identification relies on centralised training, but federated learning (FL) offers a privacy-preserving alternative, enabling collaborative model training without sharing raw data. FL enhances edge devices' ability to identify previously unconnected devices. However, resource constraints like limited computation, power, and communication capabilities may prevent some edge devices from actively participating in FL. We propose a solution where resource-limited IoT devices benefit from FL by subscribing to server-based services. This work presents an efficient AI model implementation for IoT device identification on embedded edge devices, detailing the toolflow from model generation to hardware implementation. We apply and evaluate various model optimisation techniques to balance performance and resource trade-offs, offering insights to advance edge-AI and scalable FL-based ML applications for IoT networks.
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    Design of a tunable delay line with on-chip calibration to generate process-invariant PWM signal for in-memory computing
    (Springer, 2023-06) Shenoy, Meetha V.; Chaturvedi, Nitin
    The recent compute-in-memory (CiM) architectures are proposed as a promising solution to support Deep Neural Network and Convolutional Neural Network to solve large and complex tasks in various machine learning applications. The CiM architecture overcomes the limitation of the current Von-Neumann architecture by performing logic computations within the memory also called as in-memory computing. In most CiM, the in-memory logic operations are performed on the weights stored in memory using the inputs that are processed through bitlines or wordlines using pulse width modulated (PWM) signals. For precise operation, the applied input signals must be stable. However, one of the main challenges faced during the input signal generation is the deviation in the width values due to process, voltage, and temperature variations. Addressing this challenge, in this work, we aim to mitigate the impact of one of these variations on the generated PWM signals. Therefore, in this work, we propose to design a tunable delay line that provides a linear PWM signal corresponding to an input vector which is further utilized to perform local computation in memory. Further, to minimize the impact of process variations, we propose an autonomous on-chip calibration circuit that dynamically tunes the delay lines to obtain stable and process-invariant pulse width modulated signals. Our simulation results for the proposed DL demonstrate a total delay of 559 psec with a delay error of less than 2% under various process corners.
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    OEAD: An Online Ensemble-based Anomaly Detection technique for RPL network
    (ACM Digital Library, 2024-01) Shenoy, Meetha V.
    Routing Protocol for Low-Power and Lossy Networks (RPL) is a widely used routing protocol in low-power and lossy networks especially when convergecast traffic is predominant. RPL routing protocol can be widely used in applications (such as smart grids, smart homes, or smart city applications) that use convergecast traffic in which nodes transmit data to a central node in a multi-hop fashion for monitoring and control purposes. However, the RPL routing protocol is prone to several attacks, and such anomalous conditions are to be identified at the earliest to prevent a network failure. Most of the recent works for anomaly detection rely on supervised machine learning techniques. A supervised network can thus only identify the categories on which it has been trained prior. Due to the wide variety of attacks to which the networks are prone, the supervised techniques are of limited use in practical applications. In this work, we propose an Online unsupervised Ensemble-based Anomaly Detection (OEAD) technique for anomaly detection. This online model can be adapted and retrained using the latest and representative traffic that reflects the current network conditions. A drift detector unit to identify significant changes in the network traffic is utilized in OEAD architecture which can update the ML model on the detection of drift in the network. The proposed OEAD technique is tested on a publicly available RADAR dataset and the results indicate that the proposed technique is promising for anomaly detection in real-time applications.
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    RPL*: An Explainable AI-based routing protocol for Internet of Mobile Things
    (Elsevier, 2024-10) Shenoy, Meetha V.
    The Internet of Mobile Things (IoMT) is an emerging paradigm of Internet of Things (IoT) with special focus on enabling mobility to the ‘things’. Several IoMT applications such as group of robots or drones performing collaborative search and rescue operation, identification of mines, warehouse management, goods delivery, etc can be considered as examples of IoMT systems. In the applications mentioned above, the nodes may send the information in a multi-hop manner to the root or coordinator node which may be static or mobile. While the Routing Protocol for Low Power and Lossy Networks (RPL) is extensively utilized in static IoT networks, it encounters significant limitations in handling mobility and providing resilience against routing attacks in mobile IoT networks. In this work, we propose a modified RPL, RPL* which is robust to handling mobility in nodes and is resilient towards routing attacks. In RPL*, any deviation from the normal behaviors of the network are identified as anomalies using an unsupervised Explainable Artificial Intelligence (XAI) strategy. In RPL*, we propose a novel mobility detection mechanism that will identify the mobility in the network in an energy efficient manner without incurring additional communication overhead. To maintain the connectivity with parent node, we propose a novel proactive connectivity management mechanism in RPL* which will ensure a smooth transition from one parent to another if required, thus avoiding the network partitioning due to mobility. The performance analysis of the system has demonstrated an improvement in packet delivery ratio of the mobile nodes by 40% due to the proposed RPL* when compared to RPL. Also, the proposed XAI strategy provided an F1-score of over 95% for the detection of sink hole and black hole attacks in the tested IoMT network scenarios. It was observed that RPL* improves the performance of the IoMT network when compared to RPL. However it may be noted that the mechanisms introduced to support mobility does not lead to a drop in PDR or increase in control packet overhead for static networks. Hence, RPL* can be considered as an alternative to RPL for IoT as well as IoMT networks.
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    Verification of Hardware Resource Utilization through High Level Synthesis for FPGA Implementation
    (IEEE, 2023) Asati, Abhijit; Shenoy, Meetha V.
    Recently, there has been a sharp rise in demand for hardware implementations because of the improved accuracy of Convolutional Neural Networks (CNN) on a wide range of classification and recognition applications. To achieve the needed performance, they include heavy processor operations and memory bandwidth. For optimized hardware deployment, which necessitates thorough optimization of system architectures and algorithms to get particularly efficient designs, a target system’s hardware resources and an estimation of its performance at a greater degree of abstraction are crucial. Since the programmable hardware fabric may be customized for each unique network, Field Programmable Gate Arrays (FPGA) can accomplish this efficiency in this situation. This paper shows the high-level synthesis (HLS) of each of the different layers of optimized CNN using the MATLAB HDL coder. Along with its HDL resource utilization report, we also investigated the computational processes and hardware resource estimation of the previously developed optimized CNN. The hardware resources required by all the convolutional and fully connected layers of the optimized CNN matches exactly will the previously calculated resources. So, the hardware resource utilization is verified through HLS. The architecture takes fixed-point math into account. All layers are synthesized in Vivado 2022.2 with the Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit as the target.
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    Convolutional Neural Network Hardware Optimization Using Bayesian Method
    (IEEE, 2024-04) Asati, Abhijit; Shenoy, Meetha V.
    Convolutional Neural Network (CNN) models have demonstrated significant benefits in the realm of computer vision and applications related to image processing. Optimizing hyperparameters in CNN models is crucial to ensuring an effective implementation of the model, whether on software, hardware, or a ‘software-hardware co-design’ platform, thereby enhancing overall performance and results. This work proposes a CNN architecture and applies the Bayesian optimization algorithm to find the best set of hyperparameter values which reduces training and recognition time both. In addition, a new parameter i.e., ‘Network optimization parameter’ (NOP) is defined which considers optimization of hardware resources for a given accuracy of the trained model. This parameter needs to be minimized which helps evaluate the best set of hyperparameter values and is essential for further implementing the CNN model in the hardware platform. The optimization is performed on both the processors, a Central Processing Unit (CPU) and a Graphical Processing Unit (GPU), in optimizing the CNN model to clearly understand the impacts of utilizing different processing units. An accuracy of 99.48 % is achieved for the Modified National Institute of Standards and Technology (MNIST) database, and an accuracy of 88.78 % is achieved for the Canadian Institute For Advanced Research (CIFAR-10) database. The proposed models are highly optimized and have lesser resource requirements (due to the lesser layer complexities and smaller filter sizes) while delivering higher accuracies compared to the available literature. Further, the calculated NOP for the proposed network is highly reduced compared to the published literature.
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    Sensor Information Processing for Wearable IoT Devices
    (Springer, 2019-11) Shenoy, Meetha V.
    Sensing technology is one of the core enablers of IoT and the improvement in sensing technology has lead to the proliferation of small form-factor, cost-effective and accurate sensors for wide variety of wearable applications. With wearable devices receiving widespread acceptance, their requirements are becoming more demanding, with the focus shifting from simple monitoring to context aware intelligent devices. This chapter presents a comprehensive description of the technical opportunities and challenges in the design of sensor information processing systems for wearables. A systematic survey of the state of the art architectures for sensor fusion for different application classes of wearable’s is presented. A discussion on design considerations for architecting sensor processing systems, including hardware, networking protocols, and algorithms at the edge, cloud level is provided. The chapter is concluded with a discussion on innovation directions in smart sensing and information processing in wearable devices.
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    A 8-bit SAR ADC using current mode approach for bio-medical applications
    (IEEE, 2014) Shenoy, Meetha V.
    This paper deals with the design of a SAR-ADC with 8-bit resolution suited for bio-medical application. The design of the key components of the SAR ADC namely, DAC, Comparator and Sample and Hold circuit (S/H) has been carried out using current mode approach with the DAC operating at sub-threshold regime. The input current range is 10nA to 2.57μA with 10nA as the LSB. The circuit has been designed in UMC 180nm technology Twin-Well Process.
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    FlexEye — A flexible camera mote for sensor networks
    (IEEE, 2015) Shenoy, Meetha V.
    In this paper the description of FlexEye - a visual sensor mote suitable of functioning as super node in the static wireless sensor networks is provided. With mobility features added on to FlexEye, the platform can be used as high performance mobile node in mobile wireless sensor networks or as a node in swarm robotics. A comparison of FlexEye with existing camera platforms developed for sensor networks is made on parameters like processing capabilities, power consumption, cost, time to prototype, support for future expansion, etc. The paper elaborates on the custom off the shelf hardware components used in design and the resource pipelined image acquisition technique implemented on the FlexEye mote for acquiring the high resolution images in real time using minimalistic resources. The paper also provides quantitative details on the achieved frame rates and power consumption details of the FlexEye platform.