Department of Electrical and Electronics Engineering
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Item Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology(Springer, 2019-02) Vidhyadharan, SanjayThis paper presents the circuit performance of an optimized TFET device whose performance is not only better than most of the TFET devices reported in current literature, but exceeds the performance of state-of-the-art industry-standard 45 nm CMOS technology. Novel TFET structures have been proposed whose ON current (Ion) matches with that of the MOSFETs, while maintaining the OFF current (Ioff) at least 3 orders of magnitude lower than the MOSFETs with the same width and at the same technology node. The key performance metrics of the optimised TFET-based circuits have been benchmarked with similar CMOS-based standard digital circuits like the simple inverter, 2 input NAND gate, 2 input NOR gate, 2 input XOR gate, 6 transistor SRAM and 3 stage inverter chain. The overall improvement in Power Delay Product (PDP) of the TFET-based circuits has been demonstrated to be more than 97% lesser than the corresponding CMOS circuits.Item Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology(Springer, 2019-02) Vidhyadharan, SanjayIn this work, the structure of a TFET device has been engineered such that it is not only better than most of the TFETs reported in literature, it’s performance is even better than the MOSFETs of the standard 45 nm CMOS technology. The device-level optimization has been discussed, in which, starting with a simple double-gate fully depleted TFET structure, the gradual improvement in device performance has been demonstrated such that the final ON current is comparable to that of the MOSFETs, while the OFF current remains at least three orders of magnitude lesser than the MOSFETs at the same 45 nm technology node. Optimization of the device structure has been carried out by studying the impact of various asymmetries in the device structure. This work is intentionally restricted only to the asymmetries which can be incorporated without any change in the standard process technology.Item TiO2−x–TiO2 Memristor Applications for Programmable Analog VLSI Circuits at 45 nm CMOS Technology Node(Springer, 2020-10) Vidhyadharan, SanjayMemristor-CMOS (MCM) technology combines CMOS processing with nano-scale memristors enabling a significant reduction in the silicon area as compared to CMOS-only counterparts. Moreover, the non-volatile memory characteristics of the memristor offers opportunity for new and innovative MCM hybrid VLSI circuits that can outperform conventional CMOS designs. MCM based hybrid, homogeneous re-configurable architectures have already gained immense popularity among digital VLSI designers. This paper explores application of TiO2−x–TiO2 charge trap memristor for programmable analog VLSI applications. The threshold adaptive memristor SPICE model has been used to evaluate the performance of the memristor in electronic design automation tool in conjunction with 45 nm CMOS devices. A digitally controlled MCM analog buffer, MCM binary phase shift keying modulator and a variable gain MCM differential amplifier has been presented in this paper. The MCM analog buffer has 81% greater gain-bandwidth product than the corresponding CMOS-only buffer and has an attenuation of −32 dB when the control signal is low. A MCM differential amplifier is proposed whose gain can be varied in both directions by shifting the operating point of the memristor through control signals, proving the advantages of using MCM technology for automatic gain control and other programmable analog VLSI applications. A MCM BPSK modulator circuit is also proposed which occupies 37.2% lesser silicon area than the conventional CMOS-only BPSK modulators, thus illustrating the utility of memristor in analog switching circuits.Item CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder(Springer, 2021-02) Vidhyadharan, SanjayThis paper proposes a carbon nanotube FET (CNFET)-based ultra-low-power dual-VDD ternary half adder (HA) circuit. The proposed design utilizes both the available ternary power supply voltages (VDD & VDD/2) and prevents direct path between the power supplies and ground, thus significantly reducing the power dissipation as compared to the conventional designs. The performance of the proposed CNFET dual-VDD HA has been compared with the same circuit implemented with 45 nm MOSFETs and also with other CNFET-based state-of-the-art HA designs proposed in the literature. The proposed HA consumes merely 86 nW of power which is significantly lesser (66–90% lower) than the power required by other ternary HA designs, and also exhibits 69–91% lower delays. The overall PDP of the proposed HA circuit is merely 4–11% of the PDP of corresponding CMOS ternary HA and other benchmarked CNFET HA designs.