Department of Electrical and Electronics Engineering
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Item An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder(Elsevier, 2021-01) Vidhyadharan, SanjayThis paper presents an ultra-low-power ternary dynamic Half Adder (HA) design which consumes merely 83 nW of power, achieving a 66–90% reduction in power consumption as compared to the other designs reported in the literature. Conventional ternary circuit designs use single VDD power supply, which is not a power-efficient technique. In these designs, the intermediate ternary logic state (VDD/2) is generated by allowing a steady-state current through two diode-connected transistors connected in series and the output is obtained from the junction of the two transistors. The proposed dual-VDD HA design utilizes both the available ternary power supply voltages (VDD & VDD/2) and prevents direct path between the power supplies and ground, in all the three possible ternary logic output states, resulting in a significant reduction in power consumption. While Carbon Nanotube FETs (CNFETs) is preferred by many researchers around the world for low-power VLSI applications, CMOS technology is still widely used in the industry because of the availability of advanced CMOS manufacturing units. Therefore, the proposed dual-VDD ternary dynamic HA design has been implemented with both CNFET and 45 nm CMOS devices. The proposed CNFET HA has an average delay of merely 8.4 ps, which is lower than the delays experienced in conventional designs (16.5–60.5 ps). The overall decrease in Power Delay Product (PDP) is 72–98% in the proposed CNFET HA, with respect to the other designs reported in the literature.Item An Efficient Ultra-Low-Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices(IEEE, 2021-01) Vidhyadharan, SanjayThis paper presents a novel ultra-low power yet high-performance device and circuit design paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs (GOTFETs) and Carbon Nanotube FETs (CNFETs). One of the distinguishing novelty reported in this work is the introduction of an innovative GOTFET device, which exhibits more than double the on-currents I on and less than 1/10 th the off-currents I off of equivalent, equally-sized mosfets at the same technology node. Most of the ternary logic designs reported earlier in the literature encode ternary bits into binary for combinational functionality and then use an Encoder to get back ternary output. Unlike the earlier designs, this paper presents a novel and significantly more efficient approach of directly designing ternary logical functions with Low V t Transistors (LVT) and High V t Transistors (HVT) using CNFET and GOTFET technologies. The new approach simplifies the design and reduces the required transistor count & interconnects, thereby reducing the delays and power consumption. The proposed Ternary Half Adder (THA) circuit, designed using CMOS, enables a 52% reduction in transistor count compared to the conventional CMOS designs available in the literature. The THA implemented with CNFET exhibits 27 ps (87% lower delay than similar CMOS design and consumes 2.4 μW power (11% lower than CMOS). On the other hand, CGOT THA exhibits 101 ps (51% lower delay than similar CMOS design) and consumes merely 1.26 μW power (53% lower than CMOS, in ultra-low power regime). The overall decrease in the Power Delay Products (PDPs) are 88% and 77%, respectively, in the proposed CNFET and CGOT THA circuits compared to the CMOS THA.Item An ultra-low-power CNFET-based improved Schmitt triggerdesign for VLSI sensor applications(Wiley, 2020-11) Vidhyadharan, SanjayTo enable easy integration of Internet of Things (IoT) sensors with digital verylarge scale integrtaion (VLSI) circuits, the interface circuits need to operateefficiently even at low power supply voltages, consuming minimum powerfrom the limited onboard supply source. Schmitt triggers have higher noisemargins and lower delays as compared to conventional static CMOS logic cir-cuits, at low-voltage levels and hence are being widely used in VLSI sensorapplications. Carbon nanotube FETs (CNFETs) haveION:IOFFandION:CGGratios significantly greater than the corresponding CMOS devices, and hencethey have been acknowledged as viable candidates to replace CMOS devices inultra-low-power VLSI circuits. This article presents an ultra-low-powerCNFET-based Schmitt trigger design, which consumes significantly lowerpower than the conventional design. The cause of the higher power consump-tion in conventional CMOS-based Schmitt trigger is the availability of a directpath betweenVDDand ground for a longer time duration, during switching.The short-circuit path in the conventional CMOS Schmitt trigger circuit is theresult of the design methodology adopted to obtain hysteresis in VTC curve.The threshold voltage of the CNFET can be easily configured by an appropri-ate selection of its chiral vector. This property of the CNFET has been used inthe implementation of a new, simple but effective Schmitt trigger, which mini-mizes the short-circuit currents, while providing the same hysteresis as that ofconventional design. The proposed circuit operates at 0.4 VVDDto cater forlow-voltage levels of VLSI sensor applications. The proposed CNFET-basedSchmitt trigger consumes only 0.002 times the power of conventional CMOSSchmitt trigger and operates 56 times faster than the conventional CMOSdesign. The overall PDP in the proposed CNFET-based Schmitt trigger hasbeen demonstrated to be merely 0.0003% of the PDP in corresponding conven-tional designsItem Mux Based Ultra-Low-Power Ternary Adders and Multiplier implemented with CNFET and 45 nm MOSFETs(Taylor & Francis, 2021-04) Vidhyadharan, SanjayThis paper presents improved multiplexer-based ultra-low-power ternary Half Adder (HA), ternary Full Adder (FA), and ternary 1-bit multiplier designs. The proposed circuits consume 61–91% lesser power and can be implemented with 10–40% lesser number of transistors, as compared to the other corresponding circuits available in the literature. The reduction in power and transistor count has been achieved through improved multiplexer designs and judicious use of pass transistor logic. CNFETs have low gate capacitance and hence are ideal devices for ultra-low-power VLSI applications; however, CMOS technology is presently the most preferred technology, because of the easy and low-cost fabrication option made available by the well-established CMOS fabrication labs. Keeping this in view, the proposed mux-based ternary half adder has been designed with both 45 nm MOSFETs and CNFETs. The performance of the proposed HA design has been benchmarked with other CNFET HA reported in the literature. The proposed mux-based CNFET ternary HA, FA and 1-bit multiplier have 10–30% lesser propagation delays than the other designs available in the literature. The reduction in the Power Delay Product (PDP) is 85–99% in the proposed mux-based CNFET ternary circuits as compared to the other benchmarked designs.Item CNFET Based Ultra-Low-Power Schmitt Trigger SRAM for Internet of Things (IoT) Applications(Springer, 2021-09) Vidhyadharan, SanjayThis paper presents Carbon Nanotube FET (CNFET) based ultra-low-power Schmitt trigger SRAM designs which can operate at voltage levels as low as 200 mV, with high Static Noise Margins (STM) of 100–120 mV. The hysteresis in the STM curve of the CNFET Schmitt SRAM has been achieved through proper adjustment of the threshold voltage Vth of the different CNFETs used to implement the SRAM. The Vth of the CNFET can be set to the required level by selecting the appropriate chiral vectors of the CNFET. The CNFET based SRAM consumes merely 3.2 pW of power as compared to 19.5 pW of power required by the same SRAM implemented with MOSFET devices. The CNFET SRAM also has an average propagation delay of 31 ps, which is significantly lower than the delay of 250 ns experienced in CMOS-based SRAM. A simplified multi-Vth 6T CNFET SRAM design is also proposed, which consumes merely 0.1 pW of power, thus enabling a 99% reduction in total power consumption in contrast to the conventional CMOS SRAM design. The device characteristics of the CNFET has been benchmarked with 45 nm CMOS devices. The improvement in the performance of the CNFET based SRAMs can be attributed to the 10 times higher ION:IOFF ratio and 18 times higher ION:CGG ratio of the CNFET as compared to the MOSFETs.Item Fast and Low-Power CMOS and CNFET based Hysteresis Voltage Comparator(Taylor & Francis, 2023-01) Vidhyadharan, SanjayThis paper presents CMOS and CNFET based hysteresis voltage comparators for low-voltage applications. The proposed CMOS and CNFET hysteresis comparators require merely 1.6 and 0.26 µW of power, respectively, which is less than one tenth of the power dissipated by the other advanced hysteresis comparators designs available in literature. The propagation delay observed in the proposed CMOS and CNFET hysteresis comparators are 162 and 47 ps, respectively, which is almost half the delay exhibited by the other hysteresis comparators. Overall, a 93–99% reduction in Power Delay Product (PDP) can be achieved. Furthermore, the proposed design requires only nine transistors compared to the 11–17 transistor requirement in conventional hysteresis comparators, thus saving up to 47% of chip area.