Department of Electrical and Electronics Engineering
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Item Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic Applications(IEEE, 2019) Vidhyadharan, SanjayFor the first time, innovative low (LVT) and high (HVT) threshold tunnel FET devices have been reported for ternary logic applications. Based on an iterative algorithm, the DG TFET structures have been optimized such that the TFET characteristics are better than the MOSFETs having same width at the standard 45 nm technology node. These devices are designed in such a way that the low and high threshold voltages are VTL = VDD/3 and VTH = 2VDD/3 respectively, with the ranges {0 to VDD/3}, {VDD/3 to 2VDD/3} & {2VDD/3 to VDD} representing the 3 logic states 0, 1 & 2 respectively. Device optimization has been carried out by studying the impact of changes in various device parameters on performance. Optimized TFET devices have been benchmarked with standard CMOS for the same circuit designed using same technology. TFET device characteristics were simulated using Synopsys TCAD tools and circuit performance benchmarking was carried out with the standard 45 nm CMOS library using cadence EDA tool. Proposed LVT & HVT TFETs have ON currents (ION) roughly twice and OFF currents (IOFF) at least an order of magnitude lower than the corresponding MOSFETs. The performance of the optimized TFET based NTI & PTI ternary logic cells have been benchmarked with analogous CMOS circuits at same technology node. The overall Power Delay Products (PDP) of the TFET based logic cells have been demonstrated to be around 99.9% lower than the corresponding CMOS based logic cells. The proposed LVT & HVT TFET based NTI and PTI cells will serve as the starting point for any ternary logic applications.Item An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET Devices(IEEE, 2019) Vidhyadharan, SanjayRecent studies have indicated that multilogic circuits in VLSI design helps in reducing the transistor count of circuits and increases the data transfer rate significantly. This paper presents an efficient design methodology for the implementation of a two bit ternary output Flash Analog to Digital Converter (ADC) utilizing Tunnel Field Effect Transistors (TFETs). Optimized SiGe TFET structures which have ON currents more than twice while OFF currents at least an order of magnitude lower than the standard 45 nm MOSFETs have been developed. These devices form the basic active elements for the proposed ADC. A new complementary TFET (CTFET) based comparator design is also proposed in the paper which has delays and power consumption lesser than the conventional CMOS based comparator design. An efficient methodology for directly designing logical functions with TFET devices, obtaining 2 bit ternary ADC output with a resolution of 50 mV and input quantized to 9 levels is illustrated in this paper. The proposed CTFET based ADC needs only 48 transistors to encode the comparator outputs to the required 2 bit ternary output which is significantly lower than the transistor count of 70 needed for the 2 bit ternary flash ADC designs available in literature. The performance of the CTFET based ternary ADC has been benchmarked with the same ADC circuit implemented with 45 nm CMOS technology. It has been demonstrated that the CTFET based ADC not only has delays much lesser than the corresponding CMOS based ADC but also consumes significantly lesser power and the overall decrease in Power Delay Product (PDP) has been shown to be 99.7%.Item Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology(Springer, 2019-02) Vidhyadharan, SanjayThis paper presents the circuit performance of an optimized TFET device whose performance is not only better than most of the TFET devices reported in current literature, but exceeds the performance of state-of-the-art industry-standard 45 nm CMOS technology. Novel TFET structures have been proposed whose ON current (Ion) matches with that of the MOSFETs, while maintaining the OFF current (Ioff) at least 3 orders of magnitude lower than the MOSFETs with the same width and at the same technology node. The key performance metrics of the optimised TFET-based circuits have been benchmarked with similar CMOS-based standard digital circuits like the simple inverter, 2 input NAND gate, 2 input NOR gate, 2 input XOR gate, 6 transistor SRAM and 3 stage inverter chain. The overall improvement in Power Delay Product (PDP) of the TFET-based circuits has been demonstrated to be more than 97% lesser than the corresponding CMOS circuits.Item Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology(Springer, 2019-02) Vidhyadharan, SanjayIn this work, the structure of a TFET device has been engineered such that it is not only better than most of the TFETs reported in literature, it’s performance is even better than the MOSFETs of the standard 45 nm CMOS technology. The device-level optimization has been discussed, in which, starting with a simple double-gate fully depleted TFET structure, the gradual improvement in device performance has been demonstrated such that the final ON current is comparable to that of the MOSFETs, while the OFF current remains at least three orders of magnitude lesser than the MOSFETs at the same 45 nm technology node. Optimization of the device structure has been carried out by studying the impact of various asymmetries in the device structure. This work is intentionally restricted only to the asymmetries which can be incorporated without any change in the standard process technology.Item A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications(Springer, 2019-06) Vidhyadharan, SanjayThis paper introduces an innovative Gate Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield double the on current Ion, while the off current Ioff remains an order lower than the analogous MOSFET having same width at the same technology node. A conventional Dynamic Comparator designed using the proposed Complementary GOTFET (CGOT) paradigm exhibits 93 ps (25%) lower delay than similar CMOS designs and consumes merely 1.11 pW (99% lower than CMOS) of static power. The overall power delay product (PDP) in the CGOT comparator design has been shown to be only 0.5% of the PDP of a conventional CMOS comparator. Although the advantages of higher Ion are manifold, however, it increases dynamic power as well. So this paper goes beyond device-level improvisation and proposes for the first time, a novel improved comparator circuit designed using the CGOT paradigm which further reduces the total power by an additional 44.5%.Item An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications(Springer, 2019-11) Vidhyadharan, SanjayAdiabatic circuits are ideally suited for implementing RFID tags and biomedical sensors due to their ultra-low power requirements. This paper presents a novel Gate Overlap Tunnel FET (GOTFET) based Advanced Adiabatic Logic which consumes upto 67% lower power than the equivalent CMOS based Symmetric Pass Gate Adiabatic Logic (SPGAL) which is the most power efficient adiabatic topology reported in recent literature. The basic building blocks of the proposed GOTFET Adiabatic Logic (GOTAL) circuits are the innovative Complementary GOTFETs (CGOT) which have twice the on state currents Ion and one order lower off state currents Ioff than the corresponding MOSFETs having same width at the same technology node. In addition to the novel devices, the novelty in the proposed design is the usage of specially engineered low threshold voltage Vt GOTFETs for minimizing non-adiabatic losses and completely avoiding the unnecessary complexity involving the generation of discharge pulse in the resetting clock circuit. Adiabatic inverter, NAND and NOR gates implemented using the proposed GOTAL circuits consume up to two orders (97%) lower power than the corresponding conventional static CMOS circuits at the same frequencies of operation under the same capacitive loads. Although adiabatic circuits are usually designed for low frequency operation, GOTAL circuits may also be used at higher frequencies owing to the improved frequency response of the CGOT devices.Item A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder(Taylor & Francis, 2020-03) Vidhyadharan, SanjayRecent researches have indicated that the gate-overlap tunnel FETs (GOTFETs) exhibit double the on-currentsIon and one-tenth the off-currents Ioff than the equally sized MOSFETs at the same technology node, making them ideal candidates for ultra-low-power VLSI applications. This paper presents a complementary GOTFET (CGOT) based dynamic full adder (DFA), which consumes significantly lower power than conventional CMOS DFAs and operates at double the speed of CMOS DFAs. A conventional DFA designed using GOTFETs instead of MOSFETs exhibits 100 ps (40%) lower & 50 ps (30%) lower delays than CMOS DFA. Furthermore, the CGOT DFA consumes merely 2.6 pW of static power, which is 99% (2 orders) lower than the corresponding CMOS DFA ., Ion, . This paper proposes a novel improved DFA circuit design, which mitigates the dynamic power by eliminating redundant switching activity within the DFA circuit, . The proposed modified DFA topology reduces the total power consumption by 25% than the conventional DFA designs at 50% switching activity. The overall power delay product (PDP) reduces to merely 0.9% of the standard CMOS designs. The total power consumption reduces even further with decreasing switching activity, and the improved CGOT DFA consumes 31% lower total power (at 25% switching activity).Item Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC(Elsevier, 2020-07) Vidhyadharan, SanjayThis paper presents a highly efficient ternary flash ADC, designed using the innovative gate-overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have on-state currents Ion more than double, while the off-state currents Ioff remaining at least an order of magnitude lower than the corresponding values of the standard 45 nm CMOS technology with the same width. Replacing MOSFETs with the proposed GOTFETs significantly reduces the static power consumption and improves performance. However, the higher Ion increases the dynamic power as well. To minimize the dynamic power, we propose a novel complementary GOTFET (CGOT) based comparator design. In addition to the inherent advantages of the GOTFET technology, the proposed design further reduces the dynamic power, such that the final power delay product (PDP) is merely 6.3% of the PDP in conventional CMOS comparator design. In addition to the novelty related to the innovative GOTFET devices, there are at least two-fold circuit-level novelty reported in this work. Firstly, we propose a novel CGOT based comparator circuit design, which, in addition to the advantages of GOTFET, further reduces the dynamic power such that the PDP is less than 1/3rd of the original PDP of the conventional comparator designed with GOTFETs. Secondly, the proposed CGOT based ADC requires only 48 transistors to encode the comparator outputs into the 2-bit ternary output, which is 30% lower than the 70 transistors necessary for the 2-bit CMOS based ternary flash ADC designs reported earlier in the literature. We propose an efficient 2-bit ternary flash ADC with a resolution of 50 mV and input quantized to 9 levels. Subsequently, we benchmark the performance of the proposed CGOT ternary flash ADC with the same ADC circuit implemented using the standard 45 nm CMOS technology library, all corresponding devices having the same width. We demonstrate that in addition to the superior performance than the corresponding CMOS ADC, the proposed CGOT ADC design consumes significantly lower power. The overall PDP of the proposed CGOT ADC is merely 6.3% of the PDP in corresponding CMOS design.Item Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node(Springer, 2020-01) Vidhyadharan, SanjayIn this paper, four different types of gate-overlap tunnel FET (GOTFET) devices are proposed for ultra-low power applications: (1) generic GOTFETs for digital logic, (2) low- and high-threshold (LVT and HVT) GOTFETs for ternary logic, (3) multi-threshold GOTFETs giving both LVT and HVT characteristics by simply altering their terminal connections and (4) line-tunneling-based GOTFETs for analog applications. The most interesting feature of the proposed GOTFET is that in the same device structure, just by changing the material and doping parameters of the device, we can get the optimal performance for different applications. Each of these GOTFET structures have been optimized such that their characteristics are superior than equally sized 45-nm MOSFETs. Device optimization has been carried out by studying the impact of changes in various device parameters on performance. GOTFET characteristics were simulated using industry-standard synopsys® TCAD tools, while the benchmarking with an equivalent CMOS technology was carried out using the standard 45-nm CMOS library in industry-standard cadence® EDA tool. Proposed GOTFETs have minimum on-state currents Ion at least twice (Ion,GOT≥2Ion,MOS), with maximum off-state currents Ioff remaining at least an order of magnitude lower (Ioff,GOT≤0.1Ioff,MOS), than the corresponding equally sized MOSFETs at the same 45-nm technology node. Circuit analysis and designs are beyond the scope of this paper; however, the innovative GOTFETs proposed in this paper will serve as the basic active devices in digital, ternary logic and analog applications yielding circuit performance far superior to the state-of-the-art designs at the same technology node, as indicated in our previous reports.Item Suppression of Ambipolar Behavior and Simultaneous Improvement in RF Performance of Gate-Overlap Tunnel Field Effect Transistor (GOTFET) Devices(Springer, 2020-07) Vidhyadharan, SanjayThis paper investigates a method to suppress the ambipolar current Iamb effectively, enhance the device performance with higher on current Ion, lower off current Ioff, lower inverse subthreshold slope SS and simultaneously improve the RF performance. Starting with a conventional double-gate TFET structure, the device optimization reported in this work has led to the gradual improvement in device performance in terms of higher Ion, lower Ioff, higher Ion/Ioff ratio and lower SS. The RF parameters of the optimized GOTFET, such as the mutual transconductance gm, gate-to-drain CGD, and gate-to-source CGS capacitances and unity-gain cut-off frequency fT are analyzed. We have optimized the tunnel FET device using the industry-standard synopsys® TCAD tools by studying the impact of various device parameters and dimensions on performance. We demonstrated that at high negative voltages, the proposed nGOTFET would completely suppress the ambipolar behavior of the device without deteriorating the device performance. We have compared the ambipolar current Iamb, Ioff, Ion, SS with 45 nm technology MOSFET and the TFETs reported earlier in literature. For the first time, we have proposed a GOTFET which completely suppresses the ambipolar current at high negative biases, without compromising the high Ion (1.04 mA/μ m) and low Ioff (0.27 pA/μ m) and low SS (32 mV/dec) at room temperature.
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