Department of Electrical and Electronics Engineering

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    Hysteresis behavior in 85-nm channel length vertical n-MOSFETs grown by MBE
    (IEEE, 1996-06) Rao, V. Ramgopal
    Vertical n-MOSFETs with channel lengths of 85 nm have been grown by MBE. For drain-to-source voltages V/sub DS/>3.3 V, these transistors exhibit hysteresis behavior similar to the reported behavior of fully depleted SOI-MOSFETs. Our results also show a gate voltage controlled turn-off of the drain current when the transistor is operating in the hysteresis mode. We have analyzed this behavior in vertical n-MOSFETs using 2-D device simulation and our results show a threshold value for the hole concentration across the source-channel junction which is required for the forward biasing of this junction. For a transistor operating in the hysteresis mode, we show that the potential barrier height for electron injection across the source-channel junction increases for increasing negative gate voltages during retrace. This results in a gate controlled turn-off of the drain current for SOI and vertical n-MOSFETs operating in the regenerative mode.
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    Border-Trap Characterization in High-κ Strained-Si MOSFETs
    (IEEE, 2007-08) Rao, V. Ramgopal
    In this letter, we focus on the border-trap characterization of TaN/HfO 2 /Si and TaN/HfO 2 /strained-Si/Si 0.8 Ge 0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-kappa films on strained- Si/Si 0.8 Ge 0.2 .These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-kappa films on strained-Si are also proposed.
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    Electret mechanism, hysteresis, and ambient performance of sol-gel silica gate dielectrics in pentacene field-effect transistors
    (IEEE, 2007-12) Rao, V. Ramgopal
    The electret induced hysteresis was studied in sol-gel silica films that result in higher drain currents and improved device performance in pentacene field-effect transistors. Vacuum and ambient condition studies of the hysteresis behavior and capacitance-voltage characteristics on single layer and varying thicknesses of bilayer dielectrics confirmed that blocking layers of thermal oxide could effectively eliminate the electret induced hysteresis, and that thin (25nm) sol-gel silica dielectrics enabled elimination of nanopores thus realizing stable device characteristics under ambient conditions.
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    Sub-50-mV Nanoelectromechanical Switch Without Body Bias
    (IEEE, 2020-09) Rao, V. Ramgopal
    This brief presents a fabricated and characterized 3-terminal (3T) nanoelectromechanical switch (NEMS) featuring for the first time a sub-50-mV pull-in voltage operation without body biasing. The proposed NEMS demonstrates a low hysteresis (<; 20 mV), low turn-on delay (15 ns), and record low subthreshold slope of 2 mV/decade due to the small air gap of only 100 nm between the gate and the source beam realized using a simple and low-cost fabrication process. NEMS is a propitious candidate toward ideal switch exhibiting a zero leakage with ON-state conductance of 0.1 A.V/μm and a sub-50-mV swing providing an ultralow active power consumption.
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    Fabrication and testing of a Hall effect based pressure sensor
    (Emerald, 2022-04) Yenuganti, Sujan
    This paper aims to present the fabrication and testing of a pressure sensor integrated with Hall effect sensors and permanent magnets arranged in two configurations to measure pressure in the range of 0–1 bar. The sensor is fabricated using stainless steel (SS) and can be used in high-temperature and highly corrosive environments. The fabricated sensor is of low cost, self-packaged and the differential arrangement helps in compensating for any ambient temperature variations.
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    On the Threshold Voltage and Performance of ZnO-Based Thin-Film Transistors with a ZrO2 Gate Dielectric
    (Springer, 2020) Gupta, Navneet; Kandpal, Kavindra; Shekhar, Chandra
    In the past few years, thin-film transistor (TFT) technology has experienced a rapid transition from amorphous silicon- (a-Si:H) and polysilicon-based TFTs to zinc oxide (ZnO)-based TFTs, and because of this transition, transparent TFTs have become a reality. In ZnO TFTs, which operate in accumulation mode, the threshold voltage has remained ambiguous due to the existence of grain boundary traps in the polycrystalline semiconducting channel. This paper provides an analytical relationship of threshold voltage with grain boundary trap density by assuming the grain boundary is a continuous onedimensional line charge. A high density of grain boundary traps leads to a high threshold voltage. However, its effect can be minimized by employing a high-j gate dielectric. In this work, we have demonstrated the reduction of threshold voltage in a ZnO TFT by using ZrO2 as a gate dielectric. A study of a ZnO/ZrO2 interface is reported by fabricating a metal–insulator–semiconductor capacitor structure. This interface is studied using capacitance–voltage (C–V) and current–voltage (I–V) characteristics. The ZnO TFT with a ZrO2 gate dielectric exhibits a low subthreshold slope (131 mV decade 1), low gate leakage current density (2.94 9 10 7 A cm 2) and low threshold voltage (1.2 V). However, it also exhibits a counterclockwise hysteresis of 1.4 V, which is attributed to the existence of oxygen vacancies.
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    Study of ZnO/BST interface for thin-film transistor (TFT) applications
    (Elsevier, 2021-04) Gupta, Navneet; Kandpal, Kavindra; Shekhar, Chandra
    This work presents an investigation of ZnO/BST interface for the potential use of (Ba,Sr)TiO3 as a gate–dielectric in ZnO based thin-film transistors (TFTs) for low-voltage operation. A metal-insulator-semiconductor capacitor (MIS-C) structure, which consists of a Pt/BST/ZnO stack, was fabricated on a corning glass substrate. The capacitance-voltage (C-V) characteristic of MIS-C gives the capacitance peak in both forward and backward sweep. This peak behavior of BST is due to its paraelectric nature attributed by changing the direction of a polar molecule over the applied electric field. C-V curve of ZnO/BST MIS-C structure exhibits a counter-clockwise hysteresis of -1.33 V due to the existence of donor-like oxygen vacancies present in BST and ZnO interface. The subthreshold slope of the device was found to be 203 mV/ decade and calculated using the measurement of interface state density (Dit). ZnO/BST interface also exhibits a very low value of leakage current density (3.148 × 10−7 Acm−2). Thus, the use of BST as a gate-dielectric in ZnO TFT has excellent potential, owing to its steep subthreshold slope, which implies fast switching and low off-state current.