Department of Electrical and Electronics Engineering
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Item Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort(IEEE, 2022-12) Mishra, NeerajA static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging-aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage (Vth) of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time ( t ). A device-level approach for Vth degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of t . A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre- and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with t to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre- and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in the Eldo SPICE environment with the 65-nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.Item Analysis of Logical Effort-Based Optimization in the Deep Submicron Technologies(Springer, 2022-12) Asati, AbhijitA convenient way to estimate and optimize the delay of VLSI digital circuits is the popular logical effort-based optimization. In this paper, we analyzed the effect of various circuit parameters such as logical effort (G), branching effort (B), electrical effort (H), and parasitic effort (P) on the delay of a given circuit for two different technology nodes, namely 180 and 16 nm. The analysis results show the variation of delay with a particular logical effort parameter. The variation between simulation delay and logical effort delay is indicated by a parameter τ’, which is compared with the τ which is the delay of an inverter driving an identical inverter with no parasitic for a chosen technology. The effectiveness of the logical effort-based optimization is explored. Further, the logical effort-based delay reduction, a super buffer-based delay reduction, and delay of an un-optimized circuit are also compared. The effect of technology on logical effort method for each parameter in the deep submicron sizes has also been investigated in this research work.Item Characterization of Logical Effort for Improved Delay(Springer, 2013) Gupta, AnuIn this paper, an effort has been made to improve the delay of a gate by skewing the gates by choosing proper sizing. The expression for skewed logical effort has been derived for universal logic gates namely NOT, NAND and NOR for minimizing the delay. The validations for minimum delay through simulation was done on a chain of inverters. The improved skewed gates showed 10% - 20% delay reduction on a chain of inverters as compared with normal skewed gate, high and low skewed gates, whereas, an improvement of 20% - 25% when compared to skewed gates favoring a particular transition. All simulations are done using Spectre in Cadence environment in UMC90nm CMOS technology at 1V power supply.Item Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology(Springer, 2013) Gupta, AnuTradeoff between the power dissipation and speed is one of the major issues in modern VLSI circuit design. Improving the circuit speed methods typically lead to excessive power consumption. In this work, we explore the energy-delay design in CMOS circuits, to find gate sizes which produce the lowest possible energy and delay. Our analysis methods include delay minimization using logical effort, formulating energy relationship with logical effort model and then optimizing the energy-delay using optimization technique. Thus, we introduce the Energy-Delay-Gain (EDG) to measure the energy reduction rate for each delay increase that is acceptable by the designer. The simulation is done using Spectre in cadence environment in UMC90nm CMOS technology.Item A comparative analysis of power and delay optimise digital logic families for high performance system design(Inder Science, 2013-12) Gupta, AnuIn this paper, we propose a high performance system design methodology taking the best average delay on prime. Our analysis method is based on the commonly used logical effort methodology, extended to the least delay to find the transistors sizing. Simulation results are tabulated using SPECTRE in 0.18 µm CMOS technology as applied to three different logic styles including static CMOS, pseudo-NMOS and skewed logic. We observe that NAND based pseudo-NMOS logic design having NMOS width as 1 µm exhibits least delay but with enormous power dissipation, evaluated by the tool, whereas, skewed logic style response is better in terms of total power. Thus, the method used accurately shows the trade-off in power-delay of a given circuit, allowing a designer to choose the most appropriate logic style.Item Design of Logical Effort for Worst Case Power Estimation in a CMOS Circuit in 90 nm Technology(IJAEE, 2012) Gupta, AnuThe Logical Effort model is mainly to reduce delay in a circuit, but does not show how to minimize power and area. This paper deals with an empirical modeling and design of logical effort for estimating power in CMOS logic gates. The power is estimated in a circuit using the power of standard inverter and the relationship established between Power (P) and Logical Effort (g), Electrical Effort (h) and Parasitic (p) have been proposed in this paper. To verify the above model a full adder circuitry producing just the carry-out in UMC 90nm CMOS technology having supply voltage of 1V is selected. The results obtained from the model are accurate to 85.5% of the values obtained. The tool used is cadence and the simulation is performed using spectre.