Department of Electrical and Electronics Engineering
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Item Design and Characterization of Bulk Driven MOS Varactor based VCO at Near Threshold Regime(IEEE, 2018-10) Mishra, NeerajA wide tuning range, low VCO gain and a low PVT variations are the requirements for Ring Oscillators at near threshold voltages (NTV). Current starved ring oscillators (CSRO) have voltage headroom issues in NTV regime. A MOS varactor based single ended ring oscillator (SERO) is best suited for its full swing characteristics, wide tuning range and low power consumption. However, a high VCO gain and nonlinearity are its limitations. This paper proposes a bulk driven MOS varactor based SERO (BD-MOS) that gives low VCO gain and a linear tuning from 0 to VDD in NTV regime. Post layout simulations have been performed on parasitic extracted netlist using HSPICE in industrial 65nm CMOS process design kit (PDK). The design is based on an analysis of MOS varactor capacitance done using 2D-Synopsis TCAD mixed-mode simulations.Item MOS Varactor RO Architectures in Near Threshold Regime Using Forward Body Biasing Techniques(IEEE, 2019-05) Mishra, NeerajDue to small output swings and series stack transistors, Differential Ring Oscillators (DRO) and current starved ROs are not well suited for Near Threshold Voltage (NTV) regime. MOS varactor based Single Ended Ring Oscillators (SERO) is well suited in NTV regime as it gives full swing characteristics, wide tuning range and has very low power consumption. This paper proposes different architectures using MOS Varactor SERO (VBRO) that gives high oscillation frequency, wide tuning range, low area and power consumption without degrading the phase noise as compared to existing VCO topologies in NTV regime. The improvement in the tuning range of the VCO is because of the change in body capacitance of the DTMOS configuration used in the VBRO. The change in the center frequency with PVT variations is compared with that of an NTV DRO. Post layout simulations have been performed on parasitic extracted netlist using HSPICE in industrial 65nm CMOS Process Design Kit (PDK). Our VBRO architecture has tuning range of 0.425 - 2.13 GHz with phase noise of -95dBc/Hz at 0.6V supply. The power consumption is only 127μW and the Figure Of Merit (FOM) is 164.96dBc/Hz.Item An Efficient and Accurate Variation-Aware Design Methodology for Near-Threshold MOS-Varactor-Based VCO Architectures(IEEE, 2020-11) Mishra, NeerajIn this article, a variation-aware design methodology for high-performance MOS-varactor voltage-controlled ring oscillator (MV-VCRO) in near-threshold-voltage (NTV) regime is proposed. The MV-VCRO is suitable because it eliminates series-stack transistors and generates rail-to-rail swing. For the first time, delay-models for conventional, bulk-driven (BD), and dynamic-threshold (DT) MV-VCROs considering nonlinearity in NTV regime is presented using effective drive current ( I eff ) and MOS-varactor capacitance models. The proposed design methodology is intuitive and considers process-voltage-temperature (PVT) variations at an initial stage of the design for width-length optimization. The methodology is highly efficient and does not require performing time-consuming Monte-Carlo (MC) simulations at post-layout stages. Look-up tables (LUTs) for MOS-varactor average-capacitances, and I eff are generated while considering the regions of device operation during MV-VCRO output-node transitions while extracting the model parameters from one-time simulations. This approach is physics/topology-based and is verified in HSPICE and Sentaurus 2-D-TCAD simulations using STM65nm and 32 nm, respectively. The I eff -models predict the oscillation frequency ( f OSC ) with an accuracy of 97%, 96%, 97% for conventional, BD, DT-MV-VCRO, respectively. Furthermore, our estimated LUT- I eff -capacitance models account for the change in f OSC , tuning range, and voltage-controlled oscillator (VCO)-gain with PVT variations with an accuracy-efficiency of 96%-99% compared to MC simulations. Furthermore, using LUTs, phase-noise, power consumption, and layout-area optimization technique is presented for a particular f OSC . Finally, the design methodology ensures that the desired f OSC is within the “linear” range of the VCO's-gain due to statistical variation of V th , V DD , etc. This ensures resilience to PVT variations for NTV-VCO in linear feedback systems.